Proceedings 12th International Symposium on System Synthesis最新文献_第2页

A graph theoretic approach for design and synthesis of multiplierless FIR filters 无乘法器FIR滤波器设计与合成的图论方法

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814266

K. Muhammad, K. Roy

{"title":"A graph theoretic approach for design and synthesis of multiplierless FIR filters","authors":"K. Muhammad, K. Roy","doi":"10.1109/ISSS.1999.814266","DOIUrl":"https://doi.org/10.1109/ISSS.1999.814266","url":null,"abstract":"We present a novel approach which can be used to obtain multiplierless implementations of finite impulse response (FIR) digital filters. The main idea is to reorder filter coefficients such that an implementation based on differential coefficients requires only a few adders. We represent this problem using a graph in which vertices represent the coefficients and edges represent the resources required when the differential coefficient corresponding to the edge is used in a computation. We also present a graph model for an implementation based on second-order coefficient differences. The optimal solution to the coefficient reordering problem is the well known problem of finding the Hamiltonian path of smallest weight in this graph. We use two approaches to find the smallest weight Hamiltonian cycle; a greedy approach, and the heuristic algorithm proposed by Lin and Kernighan. The power and potential of this approach is demonstrated by presenting results for large filters (lengths up to >300) which show that, in general, for 18-bit coefficients, the total number of adders required per coefficient is less than 2. Hence, high performance and/or low power filters can be designed and synthesized using the proposed approach.","PeriodicalId":185946,"journal":{"name":"Proceedings 12th International Symposium on System Synthesis","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions RTGEN:一种从体系结构描述自动生成预订表的算法

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814259

P. Grun, A. Halambi, N. Dutt, A. Nicolau

引用次数: 50

Automatic architectural synthesis of VLIW and EPIC processors VLIW和EPIC处理器的自动体系结构综合

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814268

Shail Aditya, B. R. Rau, V. Kathail

{"title":"Automatic architectural synthesis of VLIW and EPIC processors","authors":"Shail Aditya, B. R. Rau, V. Kathail","doi":"10.1109/ISSS.1999.814268","DOIUrl":"https://doi.org/10.1109/ISSS.1999.814268","url":null,"abstract":"The paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing (EPIC) processor architectures starting from an abstract specification of their desired functionality. The process of architecture design makes concrete decisions regarding the number and types of functional units, number of read/write ports on register files, the datapath interconnect, the instruction format, its decoding hardware, and the instruction unit datapath. The processor design is then automatically synthesized into a detailed RTL-level structural model in VHDL, along with an estimate of its area. The system also generates the corresponding detailed machine description and instruction format description that can be used to retarget a compiler and an assembler respectively. All this is part of an overall design system, called Program-In-Chip Out (PICO), which has the ability to perform automatic exploration of the architectural design space while customizing the architecture to a given application and making intelligent, quantitative, cost-performance tradeoffs.","PeriodicalId":185946,"journal":{"name":"Proceedings 12th International Symposium on System Synthesis","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 76

System synthesis of synchronous multimedia applications 系统综合同步多媒体应用

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814271

G. Qu, M. Mesarina, M. Potkonjak

{"title":"System synthesis of synchronous multimedia applications","authors":"G. Qu, M. Mesarina, M. Potkonjak","doi":"10.1109/ISSS.1999.814271","DOIUrl":"https://doi.org/10.1109/ISSS.1999.814271","url":null,"abstract":"Modern system design is being increasingly driven by applications such as multimedia and wireless sensing and communications, which all have intrinsic quality of service (QoS) requirements, such as throughput, error-rate, and resolution. One of the most crucial QoS guarantees that the system has to provide is the timing constraints among the interacting media (synchronization) and within each media (latency). We have developed the first framework for systems design with timing QoS guarantees, latency and synchronization. In particular we address how to design system-on-chip with minimal silicon area to meet timing constraints. We propose the two-phase design methodology. In the first phase, we select an architecture which facilitates the needs of synchronous low latency applications well. In the second phase, for a given processor configuration, we use our new scheduler in such a way that storage requirements are minimized. We have developed scheduling algorithms that solve the problem optimally for a-priori specified applications. The algorithms have been implemented and their effectiveness demonstrated on a set of simulated MPEG streams from popular movies.","PeriodicalId":185946,"journal":{"name":"Proceedings 12th International Symposium on System Synthesis","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A framework for scheduling and context allocation in reconfigurable computing 可重构计算中的调度和上下文分配框架

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814272

R. Maestre, Milagros Fernández, R. Hermida, N. Bagherzadeh

引用次数: 21

Path-based edge activation for dynamic run-time scheduling 动态运行时调度的基于路径的边缘激活

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814257

V. Mooney

引用次数: 3

Exploration and synthesis of dynamic data sets in telecom network applications 电信网络应用中动态数据集的探索与综合

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814265

C. Ykman-Couvreur, Jurgen Lambrecht, D. Verkest, F. Catthoor, H. Man

引用次数: 12

Pre-fetching for improved core interfacing 预取改进的核心接口

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814260

Roman L. Lysecky, F. Vahid, Rilesh Patel, T. Givargis

引用次数: 9

Real-time task scheduling for a variable voltage processor 可变电压处理器的实时任务调度

Proceedings 12th International Symposium on System Synthesis Pub Date : 1998-12-11 DOI: 10.1109/ISSS.1999.814256

T. Okuma, T. Ishihara, H. Yasuura

引用次数: 99