Proceedings 12th International Symposium on System Synthesis最新文献

A buffer merging technique for reducing memory requirements of synchronous dataflow specifications 一种缓冲区合并技术，用于减少同步数据流规范的内存需求

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814264

P. Murthy, S. Bhattacharyya

引用次数: 18

Catalyst: a DSIP design flow development in industry 催化剂:DSIP设计流程在工业上的发展

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814270

W. D. Rammelaere, K. Eckert, T. Lawell, R. McGarity, F. Steininger, P. L. Moenner, E. Hilkens

引用次数: 1

Loop alignment for memory accesses optimization 内存访问优化的循环对齐

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814263

A. Fraboulet, Guillaume Huard, A. Mignotte

引用次数: 60

Compressed code execution on DSP architectures 在DSP架构上压缩代码执行

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814261

P. Centoducatte, Ricardo Pannain, G. Araújo

引用次数: 14

Efficient scheduling of DSP code on processors with distributed register files 分布式寄存器文件处理器上DSP代码的高效调度

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814267

B. Mesman, C. A. Pinto, Koen van Eijk

引用次数: 17

Event-driven power management of portable systems 便携式系统的事件驱动电源管理

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814255

T. Simunic, G. Micheli, L. Benini

引用次数: 77

Bit-width selection for data-path implementations 数据路径实现的位宽选择

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814269

C. Carreras, Juan A. López, O. Nieto-Taladriz

引用次数: 32

Middleware techniques and optimizations for real-time, embedded systems 实时嵌入式系统的中间件技术和优化

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814254

D. Schmidt

{"title":"Middleware techniques and optimizations for real-time, embedded systems","authors":"D. Schmidt","doi":"10.1109/ISSS.1999.814254","DOIUrl":"https://doi.org/10.1109/ISSS.1999.814254","url":null,"abstract":"Due to constraints on footprint, performance, and weight/power consumption, real time, embedded system software development has historically lagged mainstream software development methodologies. As a result, real time, embedded software systems are costly to evolve and maintain. Moreover, they are often so specialized that they cannot adapt readily to meet new market opportunities or technology innovations. To further exacerbate matters, a growing class of real time, embedded systems require end-to-end support for various quality of service (QoS) aspects, such as bandwidth, latency, jitter, and dependability. These applications include telecommunication systems (e.g., call processing and switching), avionics control systems (e.g., operational night programs for fighter aircraft), and multimedia (e.g., Internet streaming video and wireless PDAs). In addition to requiring support for stringent QoS requirements, these systems are often targeted at highly competitive markets, where deregulation and global competition are motivating the need for increased software productivity and quality. Requirements for increased software productivity and quality motivate the use of Distributed Object Computing (DOC) middleware (A. Gokhale and D.C. Schmidt, 1999). Middleware resides between client and server applications and services in complex software systems. The goal of middleware is to integrate reusable software components to decrease the cycle time and effort required to develop high quality real time and embedded applications and services.","PeriodicalId":185946,"journal":{"name":"Proceedings 12th International Symposium on System Synthesis","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs 从多速率数据流图中优化了复杂RT级构建块的系统合成

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814258

J. Horstmannshoff, H. Meyr

{"title":"Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs","authors":"J. Horstmannshoff, H. Meyr","doi":"10.1109/ISSS.1999.814258","DOIUrl":"https://doi.org/10.1109/ISSS.1999.814258","url":null,"abstract":"In order to cope with the ever increasing complexity of today's application specific integrated circuits, a building block based design methodology is established. The system is composed of high level building blocks, of which some are reused from previous designs while others might have been created by behavioral synthesis. In data flow oriented designs, these blocks usually have complex non-matching interface properties, making it necessary to generate additional interfacing and controlling hardware to integrate them into an operable system. An RTL-HDL code generation from a synchronous data flow representation is introduced, that efficiently automates the generation of the required additional hardware. While existing code generation approaches provide strong limitations concerning the building block interfacing properties, our method enables the integration of components that access their ports periodically with arbitrary patterns. In order to reduce interface register cost, a minimum-area retiming approach is taken to determine optimum building block activation times, which is known to have polynomial time complexity. The code generation methodology is compared to an existing approach using a simple case study.","PeriodicalId":185946,"journal":{"name":"Proceedings 12th International Symposium on System Synthesis","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133119068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Loop scheduling and partitions for hiding memory latencies 用于隐藏内存延迟的循环调度和分区

Proceedings 12th International Symposium on System Synthesis Pub Date : 1999-11-01 DOI: 10.1109/ISSS.1999.814262

Fei Chen, E. Sha

引用次数: 18