2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop最新文献

IO latency hiding in pipelined architectures 隐藏在流水线架构中的IO延迟

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614345

Sam Siewert

引用次数: 3

Multiple-description PCM speech coding by complementary asymmetric vector quantizers 基于互补非对称矢量量化器的多描述PCM语音编码

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614348

S. Voran

引用次数: 0

Automatic detection of high frequency epileptiform oscillations from intracranial EEG recordings of patients with neocortical epilepsy 新皮质癫痫患者颅内脑电图记录高频癫痫样振荡的自动检测

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614347

O. Smart, Greg Worrell, George Vachtsevanos, Brian Litt

引用次数: 21

Closed-loop adaptive supply voltage scaling controller for low-power embedded processors 用于低功耗嵌入式处理器的闭环自适应电源电压缩放控制器

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614339

S. Dhar, G. Mortensen

引用次数: 2

An embedded real-time autonomic architecture 嵌入式实时自治架构

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614346

Sam Siewert, Z. Pfeffer

引用次数: 2

The design of a polishing procedure for investigating profiles formed by DRIE to fabricate through-silicon vias 设计了一种抛光程序，用于研究由DRIE形成的轮廓，以制造硅通孔

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614341

D. McBride, S. Polamreddy, S. Burkett, L. Schaper

引用次数: 0

A time linear arrival approach to the control of flexible structures 柔性结构控制的时间线性到达方法

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614338

C. Cutforth, A. Naik

引用次数: 0

A concurrent processing approach for software defined radio baseband design 软件定义无线电基带设计的并发处理方法

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614342

H. Myler, S.A. Bagasrawala, N. V. Narayana

{"title":"A concurrent processing approach for software defined radio baseband design","authors":"H. Myler, S.A. Bagasrawala, N. V. Narayana","doi":"10.1109/TPSD.2005.1614342","DOIUrl":"https://doi.org/10.1109/TPSD.2005.1614342","url":null,"abstract":"In this paper, we present a transceiver architecture that incorporates an ultra-high performance software programmable SIMD based processor for digital communications in order to perform many of the intensive baseband processing modules required by a software defined radio (SDR). The parallel processor is used as the core of the transceiver and its usage for physical layer functions in wireless communications is evaluated. The parallel core consists of an array of identical processing elements and a reconfigurable intercommunication network for concurrent data processing. Complete high level software programmability of the core provides the desired flexibility over ASIC based systems and may reduce the time-to-market period and overall design costs. The array-based architecture also addresses the high speed performance requirements typically lacking in DSP architectures for processing realtime data streaming from the RF front end. It also matches FPGA technology in terms of raw performance while incorporating complete reconfigurability to realize the goal of multimode systems.","PeriodicalId":185834,"journal":{"name":"2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125154513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Testing of fixed broadband wireless systems at 5.8 GHz 5.8 GHz固定宽带无线系统测试

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614344

T. Schwengler, N. Pendharkar

引用次数: 11

Design of a VLSI FPGA integrated circuit VLSI FPGA集成电路的设计

2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop Pub Date : 2005-04-07 DOI: 10.1109/TPSD.2005.1614340

J. Malik, A. Ojha

{"title":"Design of a VLSI FPGA integrated circuit","authors":"J. Malik, A. Ojha","doi":"10.1109/TPSD.2005.1614340","DOIUrl":"https://doi.org/10.1109/TPSD.2005.1614340","url":null,"abstract":"Field programmable gate arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. In addition to their usefulness as mentioned above, their internal structure also makes them as a suitable vehicle to learn all aspects of VLSI design because they consist of combinational logic in the form of LUT (look up table), flip-flops as sequential building blocks, and memory for programmability. VLSI design requires a careful forethought about the entire design process with special attention to floorplanning, layout, routing, transistor sizing, clock and power distribution, and timing analysis. This paper describes all these aspects of VLSI design as applied to the design of a simple FPGA that was designed as an individual project in a VLSI class. The size of the FPGA was restricted to the one that could fit into the MOSIS 40-pin TinyChip padframe. The FPGA consisted of 3-input LUTs as configurable logic blocks, and a chain of shift registers to hold the configuration bits. In addition, output flip-flops were also provided so that a state machine could be implemented in the FPGA. Circuit details of the components are provided in this paper. The layout of the FPGA was done using Magic, and its performance was verified using the IRSIM digital simulator. Finally, the FPGA was programmed to build a traffic light controller. The design process served as a very useful tool to learn about VLSI design since it encompassed all possible aspects of a complex VLSI design.","PeriodicalId":185834,"journal":{"name":"2005 IEEE Region 5 and IEEE Denver Section Technical, Professional and Student Development Workshop","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123360423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9