{"title":"A Study of Optimal Cost-Skew Tradeoff and Remaining Suboptimality in Interconnect Tree Constructions","authors":"Kwangsoo Han, A. Kahng, C. Moyes, A. Zelikovsky","doi":"10.1145/3225209.3225215","DOIUrl":"https://doi.org/10.1145/3225209.3225215","url":null,"abstract":"Cost and skew are among the most fundamental objectives for interconnect tree synthesis. The cost-skew tradeoff is particularly important in buffered clock tree construction, where clock subnets are an important “sweet spot” for balancing on-chip variation-aware analysis, skew, power and other factors. In advanced nodes, where both performance and power are critical to IC products, there is a renewed challenge of minimizing wirelength while controlling skew. In this work, we formulate the minimum-cost bounded skew spanning and Steiner tree problems as flow-based integer linear programs, and give the first-ever study of optimal cost-skew tradeoffs. We also assess heuristics (notably, Bounded-Skew DME (BST-DME), Steiner shallow-light tree (SALT), and Prim-Dijkstra (PD)) that are currently available for trading off cost and skew. Experimental results demonstrate that BST-DME has suboptimality ~ 10% in cost at iso-skew and ~ 50% in skew at iso-cost. In addition, SALT and PD shows suboptimality in terms of skew by up to ~3×.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133931648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Resource and Data Optimization for Hardware Implementation of Deep Neural Networks Targeting FPGA-based Edge Devices","authors":"Xinheng Liu, Dae-Hee Kim, Chang Wu, Deming Chen","doi":"10.1145/3225209.3225214","DOIUrl":"https://doi.org/10.1145/3225209.3225214","url":null,"abstract":"Recently, as machine learning algorithms have become more practical, there has been much effort to implement them on edge devices that can be used in our daily lives. However, unlike server-scale devices, edge devices are relatively small and thus have much more limited resources. Therefore, control of resource usage and hardware optimization play an important role when we implement machine learning algorithms on an edge device. In this paper, we target convolutional neural networks (CNN) and explore various optimization and design techniques to realize them on FPGA devices. The key idea explored in this paper is Backward Pipeline Scheduling together with Latency Balancing which optimize the pipeline between CNN layers in order to significantly reduce the overall latency for processing a single image. We also develop a batch processing design to improve the throughput of the FPGA solution. We have achieved latency of 175.7µs for classifying one image in the MNIST data set using LeNet and 653.4µs for classifying one image in Cifar-10 data set using CifarNet. Without retraining, we are still able to maintain high accuracy of 97.6% for MNIST data set and 83.6% for the Cifar-10 data set. Our achieved single- image latency is 5.2x faster for LeNet and 1.95x faster for CifarNet compared to the NVIDIA Jetson TX1 solution.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125128996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting PDN Noise to Thwart Correlation Power Analysis Attacks in 3D ICs","authors":"Jaya Dofe, Qiaoyan Yu","doi":"10.1145/3225209.3225212","DOIUrl":"https://doi.org/10.1145/3225209.3225212","url":null,"abstract":"Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks. However, there lack extensive studies on the unique feature of 3D power distribution network (PDN) noise and its impact on the efficiency of SCA attacks in 3D chips. This work fills the gap. Our experiments based on the real PDN and through-silicon via (TSV) models indicate that the noise from the other 3D planes is additive, which can significantly change the power profile of the crytpo unit in a 3D chip. We exploit the cross-plane PDN noise to develop a new countermeasure against the correlation power analysis (CPA) attacks in 3D integrated circuits (ICs). Simulation results show that the proposed method successfully improves the system resilience against CPA attacks and enhances the correlation difference by 29.1% and 18.7% over 2D and 3D baseline, respectively.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123705615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Design Framework for Processing-In-Memory Accelerator","authors":"Di Gao, Tianhao Shen, Cheng Zhuo","doi":"10.1145/3225209.3225213","DOIUrl":"https://doi.org/10.1145/3225209.3225213","url":null,"abstract":"With increasing performance mismatch between processor and memory, “memory wall” has become the bottleneck of the entire computing system. In order to bridge the gap, processing-in-memory (PIM) has been revisited as a viable option to overcome the challenge, with various researches from devices to system. In this paper we present a complete design framework for PIM based acceleration with energy efficiency and performance improvement. The framework covers system level design and prototype architecture and software stack support to enable hardware accelerator design and optimization. It is also featured with configurability, easy access and effective evaluating and profiling. In the experiments, we analyzed a convolutional neural network to identify the least energy-efficient operation and replaced that by PIM acceleration. The experimental results show that the proposed accelerator is able to achieve up 6-9X performance gain for matrix multiplication as well as 10-15X energy improvement compared to conventional CPU-only implementation.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127190146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ilgweon Kang, Dongwon Park, C. Han, Chung-Kuan Cheng
{"title":"Fast and Precise Routability Analysis with Conditional Design Rules","authors":"Ilgweon Kang, Dongwon Park, C. Han, Chung-Kuan Cheng","doi":"10.1145/3225209.3225210","DOIUrl":"https://doi.org/10.1145/3225209.3225210","url":null,"abstract":"As pin accessibility encounters more challenges due to the less number of tracks, higher pin density, and more complex design rules, routability has become one bottleneck of sub-l0 nm designs. Thus, we need a new design methodology for fast turnaround in analyzing the feasibility of the layout architecture, e.g., design rules and patterns of pin assignment. In this paper, we propose a novel framework that efficiently identifies the design rule-correct routability by creating well-organized formulation. We start with a new SAT-friendly ILP formulation which satisfies conditional design rules. In the ILP-to-SAT conversion stage, we reduce the complexity of the SAT problem by utilizing a logic minimizer and further refining the SAT formula. We demonstrate that our framework performs the routability analysis within 0.24% of ILP runtime on average, while guaranteeing the precise assessment of the routability.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Adaptive Sensitivity Analysis with Nonlinear Power Load Modeling","authors":"Po-Ya Hsu, Chun-Han Yao, Yuwei Wang, Chung-Kuan Cheng","doi":"10.1145/3225209.3225211","DOIUrl":"https://doi.org/10.1145/3225209.3225211","url":null,"abstract":"Voltage fluctuation in power networks is a critical issue for VLSI designs. The analysis and optimization of the voltage drops rely on accurate sensitivity calculation. Due to the high complexity of large-scale circuits, in practice active devices are simplified with power load models. In order to grasp the details of voltage fluctuation, we propose a nonlinear power load model as a function of the supply voltage. We adopt an adaptive analysis algorithm to accelerate the calculation. The power load model provides efficient and accurate noise prediction at system-level.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}