A Design Framework for Processing-In-Memory Accelerator

Di Gao, Tianhao Shen, Cheng Zhuo
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引用次数: 6

Abstract

With increasing performance mismatch between processor and memory, “memory wall” has become the bottleneck of the entire computing system. In order to bridge the gap, processing-in-memory (PIM) has been revisited as a viable option to overcome the challenge, with various researches from devices to system. In this paper we present a complete design framework for PIM based acceleration with energy efficiency and performance improvement. The framework covers system level design and prototype architecture and software stack support to enable hardware accelerator design and optimization. It is also featured with configurability, easy access and effective evaluating and profiling. In the experiments, we analyzed a convolutional neural network to identify the least energy-efficient operation and replaced that by PIM acceleration. The experimental results show that the proposed accelerator is able to achieve up 6-9X performance gain for matrix multiplication as well as 10-15X energy improvement compared to conventional CPU-only implementation.
内存处理加速器的设计框架
随着处理器和内存之间性能不匹配的加剧,“内存墙”已经成为整个计算系统的瓶颈。为了弥补这一差距,从设备到系统的各种研究已经重新审视了内存处理(PIM)作为克服挑战的可行选择。在本文中,我们提出了一个完整的基于PIM的加速设计框架,以提高能效和性能。该框架涵盖了系统级设计和原型架构以及软件堆栈支持,以实现硬件加速器的设计和优化。它还具有可配置性,易于访问和有效的评估和分析的特点。在实验中,我们分析了卷积神经网络来识别最不节能的操作,并用PIM加速取代它。实验结果表明,与传统的纯cpu实现相比,所提出的加速器能够实现高达6-9倍的矩阵乘法性能提升以及10-15倍的能量改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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