互连树结构中最优成本-偏态权衡与剩余次优性研究

Kwangsoo Han, A. Kahng, C. Moyes, A. Zelikovsky
{"title":"互连树结构中最优成本-偏态权衡与剩余次优性研究","authors":"Kwangsoo Han, A. Kahng, C. Moyes, A. Zelikovsky","doi":"10.1145/3225209.3225215","DOIUrl":null,"url":null,"abstract":"Cost and skew are among the most fundamental objectives for interconnect tree synthesis. The cost-skew tradeoff is particularly important in buffered clock tree construction, where clock subnets are an important “sweet spot” for balancing on-chip variation-aware analysis, skew, power and other factors. In advanced nodes, where both performance and power are critical to IC products, there is a renewed challenge of minimizing wirelength while controlling skew. In this work, we formulate the minimum-cost bounded skew spanning and Steiner tree problems as flow-based integer linear programs, and give the first-ever study of optimal cost-skew tradeoffs. We also assess heuristics (notably, Bounded-Skew DME (BST-DME), Steiner shallow-light tree (SALT), and Prim-Dijkstra (PD)) that are currently available for trading off cost and skew. Experimental results demonstrate that BST-DME has suboptimality ~ 10% in cost at iso-skew and ~ 50% in skew at iso-cost. In addition, SALT and PD shows suboptimality in terms of skew by up to ~3×.","PeriodicalId":185773,"journal":{"name":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Study of Optimal Cost-Skew Tradeoff and Remaining Suboptimality in Interconnect Tree Constructions\",\"authors\":\"Kwangsoo Han, A. Kahng, C. Moyes, A. Zelikovsky\",\"doi\":\"10.1145/3225209.3225215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cost and skew are among the most fundamental objectives for interconnect tree synthesis. The cost-skew tradeoff is particularly important in buffered clock tree construction, where clock subnets are an important “sweet spot” for balancing on-chip variation-aware analysis, skew, power and other factors. In advanced nodes, where both performance and power are critical to IC products, there is a renewed challenge of minimizing wirelength while controlling skew. In this work, we formulate the minimum-cost bounded skew spanning and Steiner tree problems as flow-based integer linear programs, and give the first-ever study of optimal cost-skew tradeoffs. We also assess heuristics (notably, Bounded-Skew DME (BST-DME), Steiner shallow-light tree (SALT), and Prim-Dijkstra (PD)) that are currently available for trading off cost and skew. Experimental results demonstrate that BST-DME has suboptimality ~ 10% in cost at iso-skew and ~ 50% in skew at iso-cost. In addition, SALT and PD shows suboptimality in terms of skew by up to ~3×.\",\"PeriodicalId\":185773,\"journal\":{\"name\":\"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)\",\"volume\":\"66 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3225209.3225215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3225209.3225215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

成本和倾斜是互连树合成的最基本目标。在缓冲时钟树结构中,成本倾斜权衡尤为重要,其中时钟子网是平衡片上变化感知分析、倾斜、功率和其他因素的重要“最佳点”。在高性能节点中,性能和功率对IC产品都至关重要,因此在控制偏斜的同时最小化无线长度是一个新的挑战。在这项工作中,我们将最小代价有界斜生成和斯坦纳树问题描述为基于流的整数线性规划,并首次研究了最优代价-斜权衡。我们还评估了启发式方法(特别是有界偏DME (BST-DME), Steiner浅光树(SALT)和Prim-Dijkstra (PD)),这些方法目前可用于权衡成本和偏度。实验结果表明,BST-DME具有次优性,在等成本下成本约为10%,在等成本下成本约为50%。此外,SALT和PD在偏度方面表现出约3倍的次优性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Study of Optimal Cost-Skew Tradeoff and Remaining Suboptimality in Interconnect Tree Constructions
Cost and skew are among the most fundamental objectives for interconnect tree synthesis. The cost-skew tradeoff is particularly important in buffered clock tree construction, where clock subnets are an important “sweet spot” for balancing on-chip variation-aware analysis, skew, power and other factors. In advanced nodes, where both performance and power are critical to IC products, there is a renewed challenge of minimizing wirelength while controlling skew. In this work, we formulate the minimum-cost bounded skew spanning and Steiner tree problems as flow-based integer linear programs, and give the first-ever study of optimal cost-skew tradeoffs. We also assess heuristics (notably, Bounded-Skew DME (BST-DME), Steiner shallow-light tree (SALT), and Prim-Dijkstra (PD)) that are currently available for trading off cost and skew. Experimental results demonstrate that BST-DME has suboptimality ~ 10% in cost at iso-skew and ~ 50% in skew at iso-cost. In addition, SALT and PD shows suboptimality in terms of skew by up to ~3×.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信