2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)最新文献

Cyber/physical co-design in practice: Case studies in metroII 网络/物理协同设计的实践:都市ii的案例研究

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509408

Luca Rizzon, R. Passerone

引用次数: 1

Communication aware multiprocessor binding for shared memory systems 用于共享内存系统的通信感知多处理器绑定

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509438

S. Adyanthaya, M. Geilen, T. Basten, J. Voeten, R. Schiffelers

引用次数: 2

Availability analysis for synchronous data-flow graphs in mixed-criticality systems 混合临界系统中同步数据流图的可用性分析

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509431

R. Medina, Etienne Borde, L. Pautet

引用次数: 4

Hardware runtime verification of embedded software in SoPC SoPC中嵌入式软件的硬件运行验证

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509425

Dimitry Solet, Jean-Luc Béchennec, M. Briday, S. Faucou, S. Pillement

引用次数: 11

Splitting tasks for migrating real-time automotive applications to multi-core ECUs 拆分任务，将实时汽车应用程序迁移到多核ecu

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509418

Martin Lowinski, D. Ziegenbein, S. Glesner

引用次数: 16

End-to-end path delay estimation in embedded software involving heterogeneous models 涉及异构模型的嵌入式软件端到端路径延迟估计

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509427

Padma Iyenghar, Arne Noyer, Joachim Engelhardt, E. Pulvermüller, C. Westerkamp

引用次数: 5

A soft real-time scheduling framework for wireless industrial sensor actuator networks 无线工业传感器执行器网络的软实时调度框架

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509416

G. Cena, S. Scanzio, L. Seno, A. Valenzano

引用次数: 4

Automated FPGA implementations of BIP designs 自动化FPGA实现的BIP设计

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509424

Maya H. Safieddine, F. Zaraket, Mohamad Jaber, R. Kanj, M. Saghir

{"title":"Automated FPGA implementations of BIP designs","authors":"Maya H. Safieddine, F. Zaraket, Mohamad Jaber, R. Kanj, M. Saghir","doi":"10.1109/SIES.2016.7509424","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509424","url":null,"abstract":"Embedded system designs have IP components that each may be implemented as either software or realtime accelerated hardware depending on the logic and the available resources. FPGA implementations are desirable hardware implementations for embedded systems since they are reconfigurable and several IP components can be deployed on the same FPGA board. BIP is a framework that facilitates correct-by-construction design of embedded systems by leveraging (1) a component based design paradigm and (2) the separation of behavior, interaction, and priority concerns. In this paper, we present the first automated design flow that takes a BIP design into an efficient FPGA implementation. We first transform the design into a one loop program implemented in C/C++ and then take the program into a sequential circuit implemented on an FPGA. We evaluate the design flow with the ATM and Quorom designs. We compare the results in terms of efficiency and performance of the software realizations of the BIP design such as regular BIP, enhanced flat BIP, and C/C++ simulations. We rely on the BIP engine to simulate regular BIP and flat BIP. The FPGA implementation is shown to be at least 16x-30x faster than the enhanced flat BIP implementation and 7x-10x faster than the C/C++ software realization running on state-of-the-art processors. Our experiments show higher performance improvement for larger design systems.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131824559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient algorithms for memory management in embedded vision systems 嵌入式视觉系统中高效的内存管理算法

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509426

K. H. Salem, Yann Kieffer, S. Mancini

{"title":"Efficient algorithms for memory management in embedded vision systems","authors":"K. H. Salem, Yann Kieffer, S. Mancini","doi":"10.1109/SIES.2016.7509426","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509426","url":null,"abstract":"In the field of embedded vision systems, meeting the constraints on design criteria such as performance, area, and power consumption can be a real challenge. In fact, to alleviate the well known “Memory Mall”, it is mandatory to provide efficient memory hierarchies to reach usable performance for the system to be designed when it has to handle non-linear image treatments. To address this problematic, Mancini and Rousseau (Proc.DATE, 2012) have designed a software generator of memory hierarchies for each non-linear image operation. It allows one to improve dramatically the performance of the system, while moderately increasing its area and energy consumption. The trade-offs between these three parameters are then taken to the level of the design of the operation of this memory hierarchy, a problem that can be formalized as a 3-objective optimization problem. In this study, we formalize this problem and give new approaches both for the problem and particular sub-problems. The results on the same real-world data set as used by Mancini and Rousseau (Proc.DATE, 2012) show a very significant improvement and reduce the amount of transferred data up to 30% and a reduction of the computing time up to 15%.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Real-time scheduling for 3D GPU rendering 实时调度3D GPU渲染

2016 11th IEEE Symposium on Industrial Embedded Systems (SIES) Pub Date : 2016-05-23 DOI: 10.1109/SIES.2016.7509411

Stephan Schnitzer, Simon Gansel, Frank Dürr, K. Rothermel

{"title":"Real-time scheduling for 3D GPU rendering","authors":"Stephan Schnitzer, Simon Gansel, Frank Dürr, K. Rothermel","doi":"10.1109/SIES.2016.7509411","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509411","url":null,"abstract":"3D graphical functions in cars enjoy growing popularity. For instance, analog instruments of the instrument cluster are replaced by digital 3D displays as shown by Mercedes-Benz in the F125 prototype car. The trend to use 3D applications expands into two directions: towards more safety-relevant applications such as the speedometer and towards third-party applications, e.g., from an app store. In order to save cost, energy, and installation space, all these applications should share a single GPU. GPU sharing brings up the problem of providing real-time guarantees for rendering content of time-sensitive applications like the speedometer. To solve this problem, we present a real-time GPU scheduling framework which provides strong guarantees for critical applications while still giving as much GPU resources to less important applications as possible, thus ensuring a high GPU utilization. Since current GPUs are not preemptible, we use the estimated execution time of each GPU rendering job to make the scheduling decisions. Our evaluations show that our scheduler guarantees given real-time constraints, while achieving a high GPU utilization of 97%. Moreover, scheduling is performed highly efficient in real-time with less than 10 μs latency.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"619 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123322748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6