Automated FPGA implementations of BIP designs

Embedded system designs have IP components that each may be implemented as either software or realtime accelerated hardware depending on the logic and the available resources. FPGA implementations are desirable hardware implementations for embedded systems since they are reconfigurable and several IP components can be deployed on the same FPGA board. BIP is a framework that facilitates correct-by-construction design of embedded systems by leveraging (1) a component based design paradigm and (2) the separation of behavior, interaction, and priority concerns. In this paper, we present the first automated design flow that takes a BIP design into an efficient FPGA implementation. We first transform the design into a one loop program implemented in C/C++ and then take the program into a sequential circuit implemented on an FPGA. We evaluate the design flow with the ATM and Quorom designs. We compare the results in terms of efficiency and performance of the software realizations of the BIP design such as regular BIP, enhanced flat BIP, and C/C++ simulations. We rely on the BIP engine to simulate regular BIP and flat BIP. The FPGA implementation is shown to be at least 16x-30x faster than the enhanced flat BIP implementation and 7x-10x faster than the C/C++ software realization running on state-of-the-art processors. Our experiments show higher performance improvement for larger design systems.