Symposium 1997 on VLSI Circuits最新文献

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Evolution Of DVD By Advanced Semiconductor Technology 先进半导体技术推动DVD的发展
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623774
Nakatsuka
{"title":"Evolution Of DVD By Advanced Semiconductor Technology","authors":"Nakatsuka","doi":"10.1109/VLSIC.1997.623774","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623774","url":null,"abstract":"The specification of the current DVD is reviewed from the view point of the semiconductor technology. LSI technology to realize signal processing and decoding/encoding as well as the laser diode requirement are described. The next generation DVD with the capacity of 15Gbytes per one side of the disc is discussed The impact of DVD to the world of multimedia is also discussed focusing on the home applications such as information home server.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"53 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114136107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS 手持PC操作系统用300MIPS全关联TLB微处理器的设计
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623776
Ishibashi, Higuchi, Shimbo, Arakawa, Nishii, Nakagawa, Maejima, Osada, Norisue, Satomura, Aoki, Shimazaki, Tanaka, Hattori, Shiozawa, Kudo, Uchiyama, Narita, Nishimoto, Nagano, Ikeda, Kuroda, Takeda, Hashimoto
{"title":"The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS","authors":"Ishibashi, Higuchi, Shimbo, Arakawa, Nishii, Nakagawa, Maejima, Osada, Norisue, Satomura, Aoki, Shimazaki, Tanaka, Hattori, Shiozawa, Kudo, Uchiyama, Narita, Nishimoto, Nagano, Ikeda, Kuroda, Takeda, Hashimoto","doi":"10.1109/VLSIC.1997.623776","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623776","url":null,"abstract":"Koichiro Ishibashi, Hisayuki Higuchi, *Yoshinobu Shimbo, Fumio Arakawa, Osamu Nishii, * *Norio Nakagawa, * *Hide0 Maejima, Kenichi Osada, *Katsunori Norisue, ***Ryuichi Satomura, **Aoki, **Yasuhisa Shimazaki, **Kazuo Tanaka, **Toshihiro Hattori, **Kenji Shiozawa, Kunio Kudo, Kunio Uchiyama, **Susumu Narita, **Junkhi Nishimoto, Takahiro Nagano, **Syuji Ikeda,**Kenichi Kuroda, Toshifumi Takeda, and **Naotaka Hashimoto","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122045957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Linearization Technique For CMOS RF Power Amplifiers CMOS射频功率放大器的线性化技术
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623823
Tanaka, Behbahani, Abidi
{"title":"A Linearization Technique For CMOS RF Power Amplifiers","authors":"Tanaka, Behbahani, Abidi","doi":"10.1109/VLSIC.1997.623823","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623823","url":null,"abstract":"","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114757239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
A 2.4-Gb/s CMOS clock recovering 1:8 demultiplexer 2.4 gb /s CMOS时钟恢复1:8解复用器
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623811
Soda, Tezuka, Shioiri, Tanabe, Furukawa, Togo, Tamura, Yoshida
{"title":"A 2.4-Gb/s CMOS clock recovering 1:8 demultiplexer","authors":"Soda, Tezuka, Shioiri, Tanabe, Furukawa, Togo, Tamura, Yoshida","doi":"10.1109/VLSIC.1997.623811","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623811","url":null,"abstract":"","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128827104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A CMOS Temperature Sensor For PowerPC RISC Microprocessors 用于PowerPC RISC微处理器的CMOS温度传感器
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623778
Hector Sanchez, R. Philip, J. Alvarez, G. Gerosa
{"title":"A CMOS Temperature Sensor For PowerPC RISC Microprocessors","authors":"Hector Sanchez, R. Philip, J. Alvarez, G. Gerosa","doi":"10.1109/VLSIC.1997.623778","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623778","url":null,"abstract":"Hector Sanchez, Ross Philip, Jose Alvarez, Gianfranco Gerosa Motorola Austin. Texas Abstract A 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described. The sensor is fully differential and based on the PTAT voltage difference between 2 diodes, yet it does not require a bandga reference. The resolution is 4OC for a temperature range of 0 C to 128OC. The offset error is 12OC over the process corners. The integral nonlinearity is below 1 LSB and the differential nonlinearity is less than 1/2 LSB. The total area of the sensor is 0.192 mm2 and the maximum power dissipation is 1OmW at 2.5V. Introduction The advent of high performance portable electronics puts increased pressure in system integrated solutions. Cost constraints, space limitations, and limited power budgets dictate the need for reducing the number of elements at the board level. External temperature sensors suffer a time-delay in the temperature reading due to the thermal constant from the integrated circuit junction to the external sensor. Furthermore, knowledge of the power consumed and the thermal resistivities is necessary to accurately determine the internal junction temperature. Integrating the temperature sensor results in a lower cost solution that minimizes board area penalty and provides more timely information to enable active thermal management. As a result, operating systems can throttle the processor or invoke a static power savings mode. [ 11","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127407036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Technology Innovations In Mobile Computers 移动计算机的技术创新
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623802
Ishida
{"title":"Technology Innovations In Mobile Computers","authors":"Ishida","doi":"10.1109/VLSIC.1997.623802","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623802","url":null,"abstract":"The demanding constraints of achieving mobilit,y in terms of size, weight, and power without compromising performance and functionality make technologies for mobile computers far more challenging than those for t,heir commodity desktop counterparts. The current success of mobile computers in the market is the result, of differentiation through countless technology innovations in components and subsystems as well as system-level integration, driven by visionary leadership in the field of mobile computing.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115547495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fifty Years Of The Transistor : The Beginning Of Silicon Technology 晶体管50年:硅技术的开端
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623775
Moll
{"title":"Fifty Years Of The Transistor : The Beginning Of Silicon Technology","authors":"Moll","doi":"10.1109/VLSIC.1997.623775","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623775","url":null,"abstract":"The first years have been somewhat controversial as to who invented the transistor. There seems to be no convergence in the disagreement as to whether Shockley or Bardeen was most responsible for the discovery of the \"transistor effect.\" Anything that I might say would not change any existing beliefs. I will give a more complete account of the next five or more years which accounted for much of the technology for the integrated circuit, and which has been largely disregarded in histories of the integrated circuit. The time from 1947 until 1952 was used to study the basic Physical behavior of germanium and silicon.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114985195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus 采用2.5V CMOS技术与3.3V LVTTL总线连接的I/0电路的动态介电保护
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623836
Connor, Evans, Braceras, Sousa, Abadeer, Hall, Robillard
{"title":"Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus","authors":"Connor, Evans, Braceras, Sousa, Abadeer, Hall, Robillard","doi":"10.1109/VLSIC.1997.623836","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623836","url":null,"abstract":"Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123963810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A Macroscopic Substrate Noise Model For Full Chip Mixed-signal Design Verification 用于全芯片混合信号设计验证的宏观衬底噪声模型
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623790
Nagata, Iwata
{"title":"A Macroscopic Substrate Noise Model For Full Chip Mixed-signal Design Verification","authors":"Nagata, Iwata","doi":"10.1109/VLSIC.1997.623790","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623790","url":null,"abstract":"","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch 一个500 MHz 32字X 64位8端口自复位CMOS寄存器文件和相关的动态到静态锁存器
Symposium 1997 on VLSI Circuits Pub Date : 1997-06-12 DOI: 10.1109/VLSIC.1997.623792
Henkels, Joshi
{"title":"A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch","authors":"Henkels, Joshi","doi":"10.1109/VLSIC.1997.623792","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623792","url":null,"abstract":"The advent of superscalar architectures for microprocessors has created the need for register files having many ports. Such multi-porting is at odds with the universal goals of high-density, high-performanc,e, and %e of testing. High-density multi-porting favors single-ended reading and wnting. However, single-ended operation makes high-performance more difficult to achieve. Another issue in VLSI is how to test the numerous embedded arrays. Typically, large memory arrays employ ABIST circuiuy. However, for small arrays, such as register files, the overhead of ABIST is more significant for performance and area, and thus is less acceptable. With this background we have set out to design a 2-write/6-read-port 32 x 64-bit register file which is dense AND fast AND readily testable in a 2.5-V 0.5-pm CMOS technology. Our approach employs self-resetting CMOS (SRCMOS) dynamic circuits [I]. Special attention has been paid toward insuring design robustness with regard to input pulsewidth variations. The testing issue has been dealt with up-front by making the memory cells totally LSSD compatible. Also designed was a dynamic-to-static latch which can be employed to make the register file compatible with either a dynamic or static dataflow.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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