{"title":"采用2.5V CMOS技术与3.3V LVTTL总线连接的I/0电路的动态介电保护","authors":"Connor, Evans, Braceras, Sousa, Abadeer, Hall, Robillard","doi":"10.1109/VLSIC.1997.623836","DOIUrl":null,"url":null,"abstract":"Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus\",\"authors\":\"Connor, Evans, Braceras, Sousa, Abadeer, Hall, Robillard\",\"doi\":\"10.1109/VLSIC.1997.623836\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].\",\"PeriodicalId\":175678,\"journal\":{\"name\":\"Symposium 1997 on VLSI Circuits\",\"volume\":\"114 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1997 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1997.623836\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1997 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1997.623836","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus
Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].
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