{"title":"Design of Wearable Textile based Microstrip-Line-Fed Antenna with Defected Ground Structure","authors":"Priyesh Jaiswal, Poonam Sinha","doi":"10.5120/cae2018652785","DOIUrl":"https://doi.org/10.5120/cae2018652785","url":null,"abstract":"By using the concept of defect ground structure (DGS) plane, a microstrip antenna is designed for C and S Band applications. The antenna is designed on polyester substrate with operating frequency 3 GHz. Defected ground structure is used to enhance the impedance bandwidth. A meander shape is integrated on the ground plane and corners are truncated. A 50 Ω microstrip feed line which behaves like a tuning stub, is used to excite the proposed antenna. The variation in the length of tuning stub affects the reflection coefficient of the proposed antenna and hence controls the return loss level as well as improves other parameters. The simulation of proposed antenna is done on IE3D tool and measure characteristics of fabricated antenna.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116667413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reduction Technique for Power Leakage in Complementary Metal Oxide Semiconductor Circuit using Deep Submicron Technology","authors":"Anjali Sharma, J. Jain","doi":"10.5120/CAE2018652779","DOIUrl":"https://doi.org/10.5120/CAE2018652779","url":null,"abstract":"Leakage power reduction has become a major factor in all modern electronic hand held and portable devices due to advancement in the scaling of all Complimentary metal oxide semiconductor devices and circuits. For the reduction of power leakage in the circuit we have used a technique to reduce leakage power at various gates. The approach used here is stack with pass transistor for reduction of leakage power in various gates in the circuit. A parallel combination of NMOS and PMOS transistor is used in parallel for enabling stacking of the transistor for leakage reduction in pull up and pull down network of the transistor. In pull up network NMOS transistor is inserted in parallel to PMOS sacked transistor to maintain Logic level 1. NMOS transistor gets connected to Vdd in pull up Network in sleep mode then pass transistor cut off which achieves a reduction of leakage of 44.63%, 44.63%, 87.02 and 87.44% at 25 Celsius as calculated in two input NAND gate. Also there is a reduction in the Average dynamic power as 15.24%, 15.28%, 35.20%, 31.20% respectively. Area, Delay and Power requirement is satisfied by choosing particular variant of NAND gate. Hence, a trade off is made among these parameters. This technique is also implemented in One bit Full Adder for Low Power leakage design of the circuit.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123113282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Unfolding Extraordinary Positive Effect of High Temperature and High Irradiance on DC Power Output of a Multicrystalline PV Module: A Case Study of Western Rajasthan","authors":"S. Garg, J. Arun","doi":"10.5120/cae2018652778","DOIUrl":"https://doi.org/10.5120/cae2018652778","url":null,"abstract":"The solar cell generates voltage when exposed to sunlight, producing direct current electricity, the power being equal to product of current and voltage. Literature and research papers shows negative temperature coefficient for both dc voltage and dc power for cell temperature greater than 25C. However, no attempt has yet been made to visualise and evaluate as to how the dc voltage, dc current and dc power varies with irradiance and temperature acting concurrently on the PV module. This paper evaluates the relative contribution of temperature and irradiance particularly POA (Plane of Array Irradiance) acting concurrently on the dc power output of a multicrystalline PV module. The cell temperature varies linearly with irradiance but due to the dominating effect of high irradiance relative to slight increase in temperature, a multicrystalline PV module gives outstanding performance at high cell temperature and high irradiance, showing remarkably overall positive effect of high cell temperature and high irradiance. In contrast to literature this paper brings forward two most vital facts. Firstly, dc power increases with increase in temperature and maximum dc voltage about 80% of its rated value is obtained at cell temperature 58.14C. Secondly, despite the negative temperature coefficient of voltage for cell temperature greater than 49C instead of 25C, significant dc voltage and dc power is obtained only for cell temperature greater than 49C. This paper also explores the input condition required to obtain high energy yield.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Traffic Density Analysis based on Image Segmentation with Adaptive Threshold","authors":"Luong Anh, T. Nguyen","doi":"10.5120/cae2018652780","DOIUrl":"https://doi.org/10.5120/cae2018652780","url":null,"abstract":"Traffic congestion has become an important problem in recent years. The main reason is the increase in the population in big cities and respective increase in number of vehicles. Traffic jams not only affect the human routine lives but also lead to a rise in the cost of transportation. So, an automatic traffic control system is required to manage the traffic congestion problem. The traffic density analysis will support the traffic management problems such as intelligent traffic signal control, traffic planning, etc. This paper has proposed a traffic density analysis method based on image segmentation with adaptive threshold. The system was designed and evaluated with the traffic images taken in Ho Chi Minh City, Viet Nam. The proposed method provides a accuracy analysis rate higher than 97% and a verification error lower than 3%.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115475173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Conventional and Modified Router Design for NOC and its FPGA Implementation","authors":"M. S.","doi":"10.5120/cae2018652775","DOIUrl":"https://doi.org/10.5120/cae2018652775","url":null,"abstract":"","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128333243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parameter optimization of Cuckoo Search Algorithm for Multi Dimensional Function Optimization Problem","authors":"M. Shafiul, Samiha Sara, S. Datta, Jannatun Razia","doi":"10.5120/CAE2018652776","DOIUrl":"https://doi.org/10.5120/CAE2018652776","url":null,"abstract":"The Cuckoo Search Algorithm is a recently developed nature inspired meta heuristic algorithm, which is established on the breeding behavior of Cuckoo species. Cuckoo search can be applied on a large variety of optimization problems. The main advantage of this search algorithm is its simplicity and better performance than many other agent or population based meta heuristic algorithms. The algorithm uses only one controlling parameter p, which makes it easier to implement and control. This parameter p, combined with the random walk mutations implemented by Lévy Flights, can control the performance and degree of exploration and exploitation of the algorithm. In this paper we have conducted a few experiments on Cuckoo Search algorithm with Lévy flights to discover the necessary conditions needed for the better performance of the algorithm. For this purpose we have taken different values of the controlling parameter p and observed the performance of the algorithm on benchmark problems, as well as its exploration and exploitation characteristics over different groups of benchmark functions.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131090452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Substrate Integrated Waveguide (SIW) Antenna","authors":"H. Amer, A. Mahmood","doi":"10.5120/cae2018652774","DOIUrl":"https://doi.org/10.5120/cae2018652774","url":null,"abstract":"The cavity-backed slots SIW antenna that suitable with planar devices is designed, simulated, implemented, and measured. The design is about of two forms of a slotted cavity at bottom side, but the microstrip line is fed at top side. The feeding line and the cavity-backed slots can be implemented on a single substrate using standard printed circuit board (PCB) process. The idea is to merge specific slot models on the cavity back side such as lateraled and meandered slots. An SIW antenna is presented, the simulation results show a 6.35 dB gain, 7.3 dB directivity, and -0.9512 dB (80.33 %) radiation efficiency, and the measurements show that the reflection coefficient (S11) at 10.2 GHz is -37.23 dB with a bandwidth of 345 MHZ (3.38 %). The combination of cavity-back slots, planar feeding, and SIW antenna design, leads to light weight, size reduction, easy implementation, and simple integration with planar circuits.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125954251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-band Circularly Polarized Microstrip Antenna for Wireless Communication","authors":"Manisha Gupta, Himani Garg","doi":"10.5120/CAE2018652772","DOIUrl":"https://doi.org/10.5120/CAE2018652772","url":null,"abstract":"The paper presents a compact monopole antenna with an integrated circularly polarized band for wireless communication. The proposed monopole antenna having a defected ground structure which uses two L-shaped slots of equal size and an unsymmetrical slot of inverted E-shaped. These slots in the ground patch are used for achieving dual band notching. The radiating patch is embedded with a staircase rectangular shape radiator( i.e. two equal square slots are detached from the lower corners). This radiating patch is used to generate the two current modes in 90 degree phase deviation and approximately equal magnitude by which circularly polarized radiation is generated. The measured results show that the proposed dual polarized monopole antenna offers a very high gain with 10 db return loss and multi notched bands, covering all the (3.1-3.5) GHz WiMAX, (5.07-6.05) GHz WLAN, (6.75-8.95) GHz X bands, (3.5-5.07)GHz C-band for satellite application.","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121120337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Global Set-Domination Number in Jump Graphs","authors":"N. Pratap, N. Swetha","doi":"10.5120/cae2018652771","DOIUrl":"https://doi.org/10.5120/cae2018652771","url":null,"abstract":"Let J(G) be a co-connected jump graph. A set D V(J(G)-D is a set dominating set (sd-set) if for every S V(J(G)-D there exists a non empty set T D such that the sub graph (S T) is connected. Further D is a global set dominating set, if D is an sd-set of both J(G) and J( ). The set domination number √s and the global set domination number √sg of J(G) are defined as expected","PeriodicalId":174733,"journal":{"name":"Communications on Applied Electronics","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}