First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)最新文献_第3页

Architectural analysis and instruction-set optimization design of network protocol processors 网络协议处理器的体系结构分析与指令集优化设计

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944703

Haiyong Xie, Li Zhao, L. Bhuyan

引用次数: 13

A fast parallel Reed-Solomon decoder on a reconfigurable architecture 基于可重构结构的快速并行里德-所罗门解码器

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944660

A. Koohi, N. Bagherzadeh, Chengzhi Pan

{"title":"A fast parallel Reed-Solomon decoder on a reconfigurable architecture","authors":"A. Koohi, N. Bagherzadeh, Chengzhi Pan","doi":"10.1145/944645.944660","DOIUrl":"https://doi.org/10.1145/944645.944660","url":null,"abstract":"This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. Numerous modifications of the first-generation of the architecture have made a scalable computation and communication intensive architecture capable of extracting parallelisms of fine grain in instruction level. Many algorithms and the whole digital video broadcasting base-band receiver as well, have been mapped onto the second architecture with impressive performance. The mapping of a Reed-Solomon decoder proposed in the paper highly parallelizes all of its sub-algorithms, including Syndrome Computation, Berlekamp Algorithm, Chein Search, and Error Value Computation, in a SIMD fashion. The mapping is tested on a cycle-accurate simulator, \"Mulate\", and the performance is encouragingly better than other architectures. The decoding speed of the RS (255,239,16) decoder using two different methods of GF multiplication can be 1.319 Gbps and 2.534 Gbps, respectively. Furthermore, since there is no functionality specifically tailored to Reed-Solomon decoder, the result has demonstrated the capability of MorphoSys architecture to extracting instruction level parallelism from streamed applications.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130836335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A modular simulation framework for architectural exploration of on-chip interconnection networks 片上互连网络架构探索的模块化仿真框架

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944648

Tim Kogel, Malte Doerper, Andreas Wieferink, R. Leupers, G. Ascheid, H. Meyr, S. Goossens

引用次数: 75

Accurate estimation of cache-related preemption delay 准确估计缓存相关的抢占延迟

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944698

H. S. Negi, T. Mitra, Abhik Roychoudhury

{"title":"Accurate estimation of cache-related preemption delay","authors":"H. S. Negi, T. Mitra, Abhik Roychoudhury","doi":"10.1145/944645.944698","DOIUrl":"https://doi.org/10.1145/944645.944698","url":null,"abstract":"Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficult. In particular, the effect of caches needs to be considered for estimating the inter-task interference. As the memory blocks of different tasks can map to the same cache blocks, preemption of a task may introduce additional cache misses. The time penalty introduced by these misses is called the cache-related preemption delay (CRPD). In this paper, we provide a program path analysis technique to estimate CRPD. Our technique performs path analysis of both the preempted and the preempting tasks. Furthermore, we improve the accuracy of the analysis by estimating the possible states of the entire cache at each possible preemption point rather than estimating the states of each cache block independently. To avoid incurring high space requirements, the cache states can be maintained symbolically as a binary decision diagram. Experimental results indicate that we obtain tight CRPD estimates for realistic benchmarks.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128480981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 113

Hardware support for real-time operating systems 实时操作系统的硬件支持

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944656

P. Kohout, B. Ganesh, B. Jacob

引用次数: 117

Early estimation of the size of VHDL projects 早期估计VHDL项目的规模

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944699

W. Fornaciari, F. Salice, D. Scarpazza

引用次数: 6

Extending the SystemC synthesis subset by object-oriented features 通过面向对象的特性扩展SystemC合成子集

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944652

E. Grimpe, F. Oppenheimer

引用次数: 41

Design optimization of mixed time/event-triggered distributed embedded systems 混合时间/事件触发分布式嵌入式系统的设计优化

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944672

T. Pop, P. Eles, Zebo Peng

引用次数: 40

Security wrappers and power analysis for SoC technology SoC技术的安全包装和功耗分析

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944689

C. Gebotys, Y. Zhang

引用次数: 32

Verification of design decisions in ForSyDe 在ForSyDe中验证设计决策

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944692

Tarvo Raudvere, I. Sander, A. Singh, A. Jantsch

引用次数: 12