First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)最新文献_第2页

A low-cost and low-power multi-standard video encoder 一种低成本、低功耗的多标准视频编码器

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944675

R. Llopis, R. Sethuraman, C. A. Pinto, H. Peters, S. Maul, M. Oosterhuis

引用次数: 9

RTOS scheduling in transaction level models 事务级模型中的RTOS调度

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944653

Haobo Yu, A. Gerstlauer, D. Gajski

引用次数: 45

A low power scheduler using game theory 使用博弈论的低功耗调度程序

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944681

N. Ranganathan, A. Murugavel

引用次数: 11

Tracking object life cycle for leakage energy optimization 跟踪目标生命周期，优化泄漏能量

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944701

Guangyu Chen, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, M. Wolczko

引用次数: 5

Architecture and synthesis for multi-cycle on-chip communication 多周期片上通信的体系结构与综合

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944667

J. Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang

{"title":"Architecture and synthesis for multi-cycle on-chip communication","authors":"J. Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang","doi":"10.1145/944645.944667","DOIUrl":"https://doi.org/10.1145/944645.944667","url":null,"abstract":"There are two important infection points in the development of deep submicron (DSM) process technologies. The first point is when the average interconnect delay exceeds the gate delay, which happened during mid 1990s and led to the so-called timing closure problem. The second point is when single-cycle full chip synchronization is no longer possible, which is about to happen soon. It can be shown that, even with the aggressive interconnect optimization techniques (e.g., buffer insertion and wire-sizing), 5 clock cycles are still needed to go from corner-to-corner for the die of 28.3 mm /spl times/ 28.3 mm in the 0.07 /spl mu/m technology generation, assuming a 5.63 GHz clock by 2006 predicted in ITRS'01 (2001). This clearly suggests that multi-cycle on-chip communication is a necessity in multi-gigahertz synchronous designs. However, it is not supported in the current design tools and methodologies, as most of these implicitly assume that full chip synchronization in a single clock cycle is feasible. Our contributions are as follows: (i) we propose a regular distributed register (RDR) microarchitecture which offers high regularity and direct support of multi-cycle communication; (ii) we develop a set of novel architectural synthesis algorithms to efficiently synthesize behavior-level designs onto the RDR architecture.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Pareto-optimization-based run-time task scheduling for embedded systems 基于pareto优化的嵌入式系统运行时任务调度

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944680

Peng Yang, F. Catthoor

引用次数: 81

A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip 片上网络中交换总线的故障模型标记和错误控制方案

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944694

H. Zimmer, A. Jantsch

引用次数: 145

Transaction level modeling: an overview 事务级建模:概述

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944651

Lukai Cai, D. Gajski

引用次数: 632

An efficient retargetable framework for instruction-set simulation 指令集仿真的有效可重定向框架

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944649

Mehrdad Reshadi, N. Bansal, P. Mishra, N. Dutt

{"title":"An efficient retargetable framework for instruction-set simulation","authors":"Mehrdad Reshadi, N. Bansal, P. Mishra, N. Dutt","doi":"10.1145/944645.944649","DOIUrl":"https://doi.org/10.1145/944645.944649","url":null,"abstract":"Instruction-set structure (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while high performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures such as RISC, CISC, VLIW and variable length instruction set processors. The instruction model is used to generate compact and easy to debug instruction descriptions that are very similar to that of architecture manual. These descriptions are used to generate high performance simulators. The generation of the simulator is completely separate from the simulation engine. Hence, we can incorporate any fast simulation technique in our retargetable framework without losing performance. We illustrate the retargetability of our approach using two popular, yet different realistic architectures: the Sparc and the ARM.","PeriodicalId":174422,"journal":{"name":"First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121221402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

The analysis and design of architecture systems for speech recognition on modern handheld-computing devices 基于现代手持计算设备的语音识别体系结构分析与设计

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) Pub Date : 2003-10-01 DOI: 10.1145/944645.944661

Andreas Hagen, D. Connors, B. Pellom

引用次数: 30