Proceedings of the 2023 International Symposium on Physical Design最新文献_第5页

Goal Driven PCB Synthesis Using Machine Learning and CloudScale Compute 目标驱动的PCB合成使用机器学习和云规模计算

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2023-03-26 DOI: 10.1145/3569052.3578907

Taylor Hogan

引用次数: 0

ISPD 2023 Lifetime Achievement Award Bio ISPD 2023终身成就奖简介

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2023-03-26 DOI: 10.1145/3569052.3586950

M. Marek-Sadowska

引用次数: 0

EDA for Domain Specific Computing: An Introduction for the Panel 面向特定领域计算的EDA:专题小组简介

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2023-03-26 DOI: 10.1145/3569052.3580221

I. Jiang, D. Chinnery

{"title":"EDA for Domain Specific Computing: An Introduction for the Panel","authors":"I. Jiang, D. Chinnery","doi":"10.1145/3569052.3580221","DOIUrl":"https://doi.org/10.1145/3569052.3580221","url":null,"abstract":"This panel explores domain-specific computing from hardware, software, and electronic design automation (EDA) perspectives. Hennessey and Patterson signaled a new \"golden age of computer architecture\" in 2018 [1]. Process technology advances and general-purpose processor improvements provided much faster and more efficient computation, but scaling with Moore's law has slowed significantly. Domain-specific customization can improve power-performance efficiency by orders-of-magnitude for important application domains, such as graphics, deep neural networks (DNN) for machine learning [2], simulation, bioinformatics [3], image processing, and many other tasks. The common features of domain-specific architectures are: 1) dedicated memories to minimize data movement across chip; 2) more arithmetic units or bigger memories; 3) use of parallelism matching the domain; 4) smaller data types appropriate for the target applications; and 5) domain-specific software languages. Expediting software development with optimized compilation for efficient fast computation on heterogeneous architectures is a difficult task, and must be considered with the hardware design. For example, GPU programming has used CUDA and OpenCL. The hardware comprises application-specific integrated circuits (ASICs) [4] and systems-of-chips (SoCs). General-purpose processor cores are often combined with graphics processing units (GPUs) for stream processing, digital signal processors, field programmable gate arrays (FPGAs) for configurability [5], artificial intelligence (AI) acceleration hardware, and so forth. Domain-specific computers have been deployed recently. For example: the Google Tensor Processing Unit (DNN ASIC) [6]; Microsoft Catapult (FPGA-based cloud domain-service solution) [7]; Intel Crest (DNN ASIC) [8]; Google Pixel Visual Core (image processing and computer vision for cell phones and tablets) [9]; and the RISC-V architecture and open instruction set for heterogeneous computing [10].","PeriodicalId":169581,"journal":{"name":"Proceedings of the 2023 International Symposium on Physical Design","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network 通过在输电网中插入额外条纹来优化电压降

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2023-03-26 DOI: 10.1145/3569052.3571870

Jai-Ming Lin, Yu-Tien Chen, Yang-Tai Kung, H. Lin

{"title":"Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network","authors":"Jai-Ming Lin, Yu-Tien Chen, Yang-Tai Kung, H. Lin","doi":"10.1145/3569052.3571870","DOIUrl":"https://doi.org/10.1145/3569052.3571870","url":null,"abstract":"As the complexity increases, power delivery network (PDN) optimization becomes a more important step in a modern design. In order to construct a robust PDN, most classic PDN optimization methods focus on adjusting the dimensions of power stripes. However, this approach becomes infeasible when voltage violation regions also have severe routing congestion. Hence, this paper proposes a delicate procedure to insert additional power stripes to reduce voltage violation while maintaining routability. In the beginning, IR-drop high related regions are identified to reveal those locations which are thirsty for more currents. Then, we solve a minimum-cost flow problem to find the topologies of power delivery paths (PDPs) from power sources to these regions and determine the widths of edges in each PDP so that enough currents can be provided to these regions. Moreover, vertical power stripes (VPSs for short) are inserted to the locations which have less routing congestion and severe voltage violations by the dynamic programming to reduce a probability to deteriorate routability. Finally, more wires will be inserted to IR-drop high related regions if there still exist voltage violations. Experimental results show that our method can use much less routing resource and induce less routing congestion to meet IR-drop constraint in industry designs.","PeriodicalId":169581,"journal":{"name":"Proceedings of the 2023 International Symposium on Physical Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126119341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Assessment of Reinforcement Learning for Macro Placement 宏观放置强化学习的评估

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2023-02-21 DOI: 10.1145/3569052.3578926

Chung-Kuan Cheng, A. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang

引用次数: 6

MQT QMAP: Efficient Quantum Circuit Mapping QMAP:高效量子电路映射

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2023-01-27 DOI: 10.1145/3569052.3578928

R. Wille, Lukas Burgholzer

引用次数: 11

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks x伏特:针对电源侧通道攻击的驱动器强度和电源电压联合调谐

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2022-11-15 DOI: 10.1145/3569052.3571882

Saideep Sreekumar, M. Ashraf, M. Nabeel, O. Sinanoglu, J. Knechtel

{"title":"X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks","authors":"Saideep Sreekumar, M. Ashraf, M. Nabeel, O. Sinanoglu, J. Knechtel","doi":"10.1145/3569052.3571882","DOIUrl":"https://doi.org/10.1145/3569052.3571882","url":null,"abstract":"Power side-channel (PSC) attacks are well-known threats to sensitive hardware like advanced encryption standard (AES) crypto cores. Given the significant impact of supply voltages (VCCs) on power profiles, various countermeasures based on VCC tuning have been proposed, among other defense strategies. Driver strengths of cells, however, have been largely overlooked, despite having direct and significant impact on power profiles as well. For the first time, we thoroughly explore the prospects of jointly tuning driver strengths and VCCs as novel working principle for PSC-attack countermeasures. Toward this end, we take the following steps: 1) we develop a simple circuit-level scheme for tuning; 2) we implement a CAD flow for design-time evaluation of ASICs, enabling security assessment of ICs before tape-out; 3) we implement a correlation power analysis (CPA) framework for thorough and comparative security analysis; 4) we conduct an extensive experimental study of a regular AES design, implemented in ASIC as well as FPGA fabrics, under various tuning scenarios; 5) we summarize design guidelines for secure and efficient joint tuning. In our experiments, we observe that runtime tuning is more effective than static tuning, for both ASIC and FPGA implementations. For the latter, the AES core is rendered > 11.8x (i.e., at least 11.8 times) as resilient as the untuned baseline design. Layout overheads can be considered acceptable, with, e.g., around +10% critical-path delay for the most resilient tuning scenario in FPGA. We release source codes for our methodology, as well as artifacts from the experimental study in[13].","PeriodicalId":169581,"journal":{"name":"Proceedings of the 2023 International Symposium on Physical Design","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124058615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Security Closure of IC Layouts Against Hardware Trojans 针对硬件木马的IC布局安全关闭

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 2022-11-15 DOI: 10.1145/3569052.3571878

Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, O. Sinanoglu, J. Knechtel, Tsung-Yi Ho, E. F. Young

{"title":"Security Closure of IC Layouts Against Hardware Trojans","authors":"Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, O. Sinanoglu, J. Knechtel, Tsung-Yi Ho, E. F. Young","doi":"10.1145/3569052.3571878","DOIUrl":"https://doi.org/10.1145/3569052.3571878","url":null,"abstract":"Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications. In this work, we proactively and systematically harden the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose a multiplexer-based logic-locking scheme that is (i) devised for layout-level Trojan prevention, (ii) resilient against state-of-the-art, oracle-less machine learning attacks, and (iii) fully integrated into a tailored, yet generic, commercial-grade design flow. Our work provides in-depth security and layout analysis on a challenging benchmark suite. We show that ours can render layouts resilient, with reasonable overheads, against Trojan insertion in general and also against second-order attacks (i.e., adversaries seeking to bypass the locking defense in an oracle-less setting). We release our layout artifacts for independent verification[29].","PeriodicalId":169581,"journal":{"name":"Proceedings of the 2023 International Symposium on Physical Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132407336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Proceedings of the 2023 International Symposium on Physical Design 2023物理设计国际研讨会论文集

Proceedings of the 2023 International Symposium on Physical Design Pub Date : 1900-01-01 DOI: 10.1145/3569052

引用次数: 1