{"title":"Robustness of Sequential Circuits","authors":"L. Doyen, T. Henzinger, Axel Legay, D. Ničković","doi":"10.1109/ACSD.2010.26","DOIUrl":"https://doi.org/10.1109/ACSD.2010.26","url":null,"abstract":"Digital components play a central role in the design of complex embedded systems. These components are interconnected with other, possibly analog, devices and the physical environment. This environment cannot be entirely captured and can provide inaccurate input data to the component. It is thus important for digital components to have a robust behavior, i.e. the presence of a small change in the input sequences should not result in a drastic change in the output sequences. In this paper, we study a notion of robustness for sequential circuits. However, since sequential circuits may have parts that are naturally discontinuous (e.g., digital controllers with switching behavior), we need a flexible framework that accommodates this fact and leaves discontinuous parts of the circuit out from the robustness analysis. As a consequence, we consider sequential circuits that have their input variables partitioned into two disjoint sets: control and disturbance variables. Our contributions are (1) a definition of robustness for sequential circuits as a form of continuity with respect to disturbance variables, (2) the characterization of the exact class of sequential circuits that are robust according to our definition, (3) an algorithm to decide whether a sequential circuit is robust or not.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127434463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Probabilistic Contracts: A Compositional Reasoning Methodology for the Design of Stochastic Systems","authors":"Benoît Delahaye, B. Caillaud, Axel Legay","doi":"10.1109/ACSD.2010.13","DOIUrl":"https://doi.org/10.1109/ACSD.2010.13","url":null,"abstract":"A contract allows to distinguish hypotheses made on a system (the guarantees) from those made on its environment (the assumptions). In this paper, we focus on models of Assume/Guarantee contracts for (stochastic) systems. We consider contracts capable of capturing reliability and availability properties of such systems. We also show that classical notions of Satisfaction and Refinement can be checked by effective methods thanks to a reduction to classical verification problems. Finally, theorems supporting compositional reasoning and enabling the scalable analysis of complex systems are also studied.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124837243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Partial Order Reduction for Branching Security Protocols","authors":"W. Fokkink, M. Dashti, Anton Wijs","doi":"10.1109/ACSD.2010.19","DOIUrl":"https://doi.org/10.1109/ACSD.2010.19","url":null,"abstract":"Two extensions of the partial order reduction algorithm of Clarke, Jha and Marrero are presented. The proposed algorithms are suitable for branching security protocols, e.g. optimistic fair contract signing schemes. The first extension is proved to generate a reduced state space which is branching bisimilar to the full state space, while the second extension generates a state space that is trace equivalent to the full state space. Experimental results using an implementation of the algorithms in the toolset of the µCRL process algebra are reported.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122274177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alban Linard, E. Paviot-Adet, F. Kordon, Didier Buchs, Samuel Charron
{"title":"polyDD: Towards a Framework Generalizing Decision Diagrams","authors":"Alban Linard, E. Paviot-Adet, F. Kordon, Didier Buchs, Samuel Charron","doi":"10.1109/ACSD.2010.17","DOIUrl":"https://doi.org/10.1109/ACSD.2010.17","url":null,"abstract":"Decision Diagrams are now widely used in model checking as extremely compact representations of state spaces. Many Decision Diagram categories have been developed over the past twenty years based on the same principles. Each one targets a specific domain with its own characteristics. Moreover, each one provides its own definition. It prevents sharing concepts and techniques between these structures. This paper aims to propose a basis for a common Framework for Decision Diagrams. It should help users of this technology to define new Decision Diagram categories thanks to a simple specification mechanism called Controller. This enables the building of efficient Decision Diagrams dedicated to a given problem.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116778190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Talpin, J. Ouy, T. Gautier, L. Besnard, A. Cortier
{"title":"Modular Interpretation of Heterogeneous Modeling Diagrams into Synchronous Equations Using Static Single Assignment","authors":"J. Talpin, J. Ouy, T. Gautier, L. Besnard, A. Cortier","doi":"10.1109/ACSD.2010.14","DOIUrl":"https://doi.org/10.1109/ACSD.2010.14","url":null,"abstract":"The ANR project SPACIFY develops a domain-specific programming environment, Synoptic, to engineer embedded software for space applications. Synoptic is an Eclipse-based modeling environment which supports all aspects of aerospace software design. As such, it is a domain-specific environment consisting of heterogeneous modeling and programming principles defined in collaboration with the industrial partners and end users of the project : imperative synchronous programs, data-flow diagrams, mode automata, blocks, components, scheduling, mapping and timing. This article focuses on the essence and distinctive features of its behavioral or programming aspects : actions, flows and automata, for which we use the code generation infrastructure of the synchronous modeling environment SME. It introduces an efficient method for transforming a hierarchy of blocks consisting of actions (sequential Esterel-like programs), data-flow diagrams (to connect and time modules) and mode automata (to schedule or mode blocks) into a set of synchronous equations. This transformation significantly reduces the needed control states and block synchronizations. It consists of an inductive static-single assignment transformation algorithm across a hierarchy of blocks that produces synchronous equations. The impact of this new transformation technique is twofold. With regards to code generation objectives, it reduces the needed resynchronization of each block in the system with respects to its parents, potentially gaining substantial performance from way less synchronizations. With regards to verification requirements, it also reduces the number of states across a hierarchy of automata and hence maximizes model checking performances.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121903716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dominic Wist, Mark Schäfer, W. Vogler, Ralf Wollowski
{"title":"STG Decomposition: Internal Communication for SI Implementability","authors":"Dominic Wist, Mark Schäfer, W. Vogler, Ralf Wollowski","doi":"10.1109/ACSD.2010.15","DOIUrl":"https://doi.org/10.1109/ACSD.2010.15","url":null,"abstract":"Logic synthesis of speed independent circuits based on STG decomposition is a promising approach to tackle complexity problems like state-space explosion. Unfortunately, decomposition can result in components that in isolation have irreducible CSC conflicts. Generalising earlier work, we show how to resolve such conflicts by introducing internal communication between the components. The new algorithms are successfully applied to some benchmarks, including very complex STGs arising in the context of control resynthesis.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125949980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wagging Logic: Implicit Parallelism Extraction Using Asynchronous Methodologies","authors":"C. Brej","doi":"10.1109/ACSD.2010.11","DOIUrl":"https://doi.org/10.1109/ACSD.2010.11","url":null,"abstract":"Asynchronous circuits have a number of potential performance advantages over their synchronous equivalents due to the ability to exploit average case performance. These advantages are offset by the loss of performance caused by the handshaking overheads which causes designs to be throughput bound. This paper investigates the nature of the throughput problem and proposes a novel automatic approach to overcome its effect. The designs generated using the method not only cease suffering from a throughput bottleneck, but also attain the parallel computation properties despite their original sequential specification. The method is then demonstrated on a processor design. The processor demonstrates the ability of the method to implement a seven gate delay per operation super scalar microprocessor with: register locking, instruction reordering, simultaneous multi-threading, cache-banking and other complex techniques, all automatically or with minor design effort. Such a design can be constructed in days rather than the hundreds of person years required by conventional methodologies.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"45 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124967591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiansheng Xing, B. Theelen, R. Langerak, J. Pol, J. Tretmans, J. Voeten
{"title":"From POOSL to UPPAAL: Transformation and Quantitative Analysis","authors":"Jiansheng Xing, B. Theelen, R. Langerak, J. Pol, J. Tretmans, J. Voeten","doi":"10.1109/ACSD.2010.21","DOIUrl":"https://doi.org/10.1109/ACSD.2010.21","url":null,"abstract":"POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control systems, POOSL has been used to construct models for performance analysis. The considered motion control algorithms are characterized by periodic execution. They are executed by multiple processors, which are interconnected by Rapid Input/Output (RapidIO) packet switches. Packet latencies as worst-case latencies and average-case latencies are essential performance criteria for motion control systems. However, POOSL analysis merely allows for estimation results for these latency metrics since it is primarily based on simulation. Because motion control systems are time-critical and safety-critical, worst-case latencies of packets are strict timing constraints. Therefore exact worst-case latencies are to be determined. Motivated by this requirement we propose to use model checking techniques. In this paper we illustrate how a POOSL model of a (simplified) motion control system can be transformed into an UPPAAL model and we verify its functional behavior and worst-case latencies. Moreover, we show that analysis of average-case latencies can also be accomplished with assistance of the model checking tool UPPAAL.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128469367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cut-Offs with Network Invariants","authors":"Antti Siirtola","doi":"10.1109/ACSD.2010.16","DOIUrl":"https://doi.org/10.1109/ACSD.2010.16","url":null,"abstract":"We consider the multi-parameterised process algebraic verification of safety properties. There is a cut-off result for such verification tasks, but it cannot be naturally applied to systems involving linear parts. We show how the limitation can be overcome by computing a network invariant for each linear part and including all the processes obtained during the computation in the system model.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133341606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Aggregation Ordering for Massively Compositional Models","authors":"P. Crouzen, H. Hermanns","doi":"10.1109/ACSD.2010.28","DOIUrl":"https://doi.org/10.1109/ACSD.2010.28","url":null,"abstract":"Compositional modeling is a powerful way of expressing the behavior of a complex system through the interaction of its components. Analysis of compositional models is difficult because of the state space explosion. One solution is compositional aggregation where composition and aggregation steps are intertwined. This approach has proven particularly useful in the area of compositional performance and dependability modelling. However, one open question remains: in which order should the models be composed, a question that is especially important for massively compositional models derived automatically from higher level descriptions. Finding the optimal composition ordering is generally infeasible, so heuristics are necessary to find good orderings. In this paper we present a comparative study of compositional aggregation algorithms which harvest and refine heuristics originating from Tai and Koppol. The heuristics take into account the interaction between components, the size of the component models and uses early elimination of bad composition orders to dramatically decrease computation time. We present an implementation of the algorithms and study its effectiveness by applying it to case studies from different application areas.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132067139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}