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Euromicro Symposium on Digital System Design, 2003. Proceedings.最新文献

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Exact numerical processing 精确数值处理
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-15 DOI: 10.1109/DSD.2003.1231978
J. Chamizo, J. M. Pascual, H. Mora
{"title":"Exact numerical processing","authors":"J. Chamizo, J. M. Pascual, H. Mora","doi":"10.1109/DSD.2003.1231978","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231978","url":null,"abstract":"A model of an exact arithmetic processing is presented. We describe a representation format that gives us a greater expressive capability and covers a wider numerical set. The rational numbers are represented by means of fractional notation and explicit codification of its periodic part. We also give a brief description of exact arithmetic operations on the proposed format. This model constitutes a good alternative for the symbolic arithmetic, in special when numerical exact values are required. As an example, we show an application of the exact numerical processing to calculate the perpendicular vector to another one for aerospace purposes.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115219972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Eccentric SoC architectures as the future norm 古怪的SoC架构将成为未来的标准
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231893
G. Brebner
{"title":"Eccentric SoC architectures as the future norm","authors":"G. Brebner","doi":"10.1109/DSD.2003.1231893","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231893","url":null,"abstract":"Reconfigurable system-on-chip (SoC) platforms are now a physical reality. This gives a system substrate which, physically at least, is fairly neutral with respect to use models and system architectures. When embedded processors are present, the most obvious use model to follow is to consider the system on chip as a scaled-down version of a system on board: we call this a processor-centric model. To provide better access to many of the benefits of the new SoC devices, we introduce an alternative logic-centric model, where the environment of a system is the driving force behind its architecture. In particular, the role of embedded processors is to assist the majority processing being carried out in logic and in input/output interfaces. We see such 'eccentric' architectures as the norm for the future, particularly given the vision of the 'disappearing computer' and the rise of 'ambient intelligence'. We illustrate the general discussion with examples drawn from our current research into systems designed for message processing.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125327850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Temperature influence on power consumption and time delay 温度对功耗和时延的影响
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231970
A. Golda, A. Kos
{"title":"Temperature influence on power consumption and time delay","authors":"A. Golda, A. Kos","doi":"10.1109/DSD.2003.1231970","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231970","url":null,"abstract":"Both the energy consumption and the propagation time delay are very critical parameters of contemporary integrated circuits. It is obvious that a circuit should consume energy as small as possible and ought to work with maximum speed and efficiency. However, these parameters are dependent on temperature, which can change with both external (e.g. high surrounding temperature) and internal (e.g. power dissipated in the circuit) conditions. The article presents the temperature influence on energy consumption and propagation time delay of CMOS ASIC circuits at the example of AMI Semiconductor 0.7 /spl mu/ CMOS C07MD technology (former Alcatel MIETEC CMOS 0.7 /spl mu/m-C07MA-C07MD). The gate was tested under the two conditions: controlled by ideal trapezoid pulse signal, and controlled by real output signal that came from previous gate.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"51 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131809370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Design and FPGA implementation of a video scalar with on-chip reduced memory utilization 片上视频标量的设计与FPGA实现，降低了内存利用率
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231927
S. Ramachandran, S. Srinivasan
{"title":"Design and FPGA implementation of a video scalar with on-chip reduced memory utilization","authors":"S. Ramachandran, S. Srinivasan","doi":"10.1109/DSD.2003.1231927","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231927","url":null,"abstract":"A novel architecture suitable for FPGA/ASIC implementation of a video scalar is presented. The scheme proposed here results in enormous savings of memory normally required, without compromising on the image quality. In the present work, SVGA compatible video sequence is scaled up to XGA format. The up scaling operation for a video sequence is carried out by scaling up the image input, followed by down scaling and filtering. The FPGA implementation of the proposed video-scaling algorithm is capable of processing high-resolution, color pictures of sizes up to 1024x768 pixels at the real time video rate of 30 frames/second. The design has been realized by RTL compliant Verilog coding, and fits into a single chip with a gate count utilization of two million gates. For lower resolution pictures, the mapped device can be scaled down. The present FPGA implementation compares favorably with another ASIC implementation.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"45 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132640085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A quadruple precision and dual double precision floating-point multiplier 四倍精度和双倍精度浮点乘法器
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231903
A. Akkas, M. Schulte
{"title":"A quadruple precision and dual double precision floating-point multiplier","authors":"A. Akkas, M. Schulte","doi":"10.1109/DSD.2003.1231903","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231903","url":null,"abstract":"Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hardware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hardware than a fully parallel quadruple precision multiplier. With this implementation, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have a latency of only two cycles. The design is pipelined so that two double precision multiplications can be started every cycle or a quadruple precision multiplication can be started every other cycle.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131251847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
NoCs: a new contract between hardware and software noc:硬件和软件之间的新合同
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231894
A. Jantsch
{"title":"NoCs: a new contract between hardware and software","authors":"A. Jantsch","doi":"10.1109/DSD.2003.1231894","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231894","url":null,"abstract":"Future single chip systems will resemble more traditional computer networks than traditional central processors. The main reasons for this trend are the infeasibility of global synchrony on a single chip, the necessity of reuse of existing hardware and software components as much as possible, and the heterogeneity and irregularity of system functions and features. The consequences of this trend are far reaching and imply the shift in concern from computation and sequential algorithms to concurrency, communication and interaction in every aspect of design and development of hardware and software. Based on an analysis of current trends we suggest that there is an opportunity for defining an interface between applications and Network-on-Chip (NoC) platform implementations with significant benefits for both worlds. We analyze the desirable properties of such an interface by means of studying a particular NoC platform, the Nostrum. We draw the general conclusion that such an interface, which we also call contract, has to include (1) description of functionality, (2) description of communication semantics and performance, and (3) mapping of task to resources.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116285927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A development and simulation environment for a floating point operations FPGA based accelerator 基于FPGA的浮点运算加速器的开发与仿真环境
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231922
M. Bera, G. Danese, I. Lotto, F. Leporati, A. Spelgatti
{"title":"A development and simulation environment for a floating point operations FPGA based accelerator","authors":"M. Bera, G. Danese, I. Lotto, F. Leporati, A. Spelgatti","doi":"10.1109/DSD.2003.1231922","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231922","url":null,"abstract":"Exploiting hardware devoted to a specific application requires a proper programming support, like libraries allowing a simple interface with the device. As a complementary design, a dedicated device language might be developed to make its programming easier. In previous works by G. Danese et al. (2002) and G. Danese et al. (2003) we presented the architecture of a floating point operations accelerator based on Field Programmable Gate Array (FPGA) technology. In this paper we describe the development environment which allows writing, translating and simulating instruction sequences written in a language specifically conceived and designed for that device.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122060016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Scheduling and assignment for real-time embedded systems with resource contention 具有资源争用的实时嵌入式系统调度与分配
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231900
Loïc Pontani, D. Dupont
{"title":"Scheduling and assignment for real-time embedded systems with resource contention","authors":"Loïc Pontani, D. Dupont","doi":"10.1109/DSD.2003.1231900","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231900","url":null,"abstract":"This paper presents a new assignment and scheduling technique for Hardware/Software partitioning in real-time embedded systems. In contrast to previous approaches, resource constraints are taken into account as soon as possible in order to reduce both the blocking time and the schedulability loss due to resource contention. The system is composed of an arbitrary number of tasks with hard real-time deadlines and different periods. Our method provides the assignment and the scheduling to hardware/software components for each sub-task of each task. Results show that our approach works for cases which cannot be dealt with other methods.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125752214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design tools and reusable libraries for FPGA-based digital circuits 基于fpga的数字电路的设计工具和可重用库
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231939
V. Sklyarov, I. Skliarova, Pedro Almeida, M. Almeida
{"title":"Design tools and reusable libraries for FPGA-based digital circuits","authors":"V. Sklyarov, I. Skliarova, Pedro Almeida, M. Almeida","doi":"10.1109/DSD.2003.1231939","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231939","url":null,"abstract":"This paper suggests tools that provide significant improvements in the design and verification of FPGA-based digital circuits. These tools include reusable specifications of hardware components (modules) that have been proposed for two types of CAD environments; Xilinx ISE 5.x and Celoxica DK1. The components can be employed to implement both application-specific blocks from the selected area (mainly from the scope of combinatorial computations) and a number of interfaces that are very useful for interaction and data exchange with devices attached to a FPGA, such as LCD and touch panels, bus controllers, etc. The designed modules can be easily integrated into any application-specific digital system and used for visualizing the results, fast data transfer, debugging of internal sub-circuits, etc. They were constructed in such a way that their functionality can be either fixed or modifiable (both statically and dynamically). The latter capability was provided with the aid of reloadable RAM-based blocks. To illustrate the capabilities of the tools suggested, four design examples are discussed. Additional materials for this paper are available in the form of a number of tutorials and projects for FPGAs that can be accessed through the Internet.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129659413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Variations on truncated multiplication 截断乘法的变体
Euromicro Symposium on Digital System Design, 2003. Proceedings. Pub Date : 2003-09-01 DOI: 10.1109/DSD.2003.1231908
J. Stine, Oliver M. Duverne
{"title":"Variations on truncated multiplication","authors":"J. Stine, Oliver M. Duverne","doi":"10.1109/DSD.2003.1231908","DOIUrl":"https://doi.org/10.1109/DSD.2003.1231908","url":null,"abstract":"Truncated multiplication can be used to significantly reduce the power dissipation for applications that do not require correctly-rounded results. This paper presents an efficient method for truncated multiplication called hybrid-correction truncation that utilizes the advantages of two previous methods to obtain lower average and maximum absolute error. Comparisons are presented contrasting power, area, and delay for all three methods compared to standard parallel multipliers. Estimates indicate that hybrid truncated multipliers dissipate slightly less power and consume slightly less area than previous methods for truncated multiplication. In addition, utilization of the hybrid truncation method can provide a method for altering the implementation within certain limits to meet a given precision.","PeriodicalId":168799,"journal":{"name":"Euromicro Symposium on Digital System Design, 2003. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127536095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
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