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ESSCIRC 80: 6th European Solid State Circuits Conference最新文献

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A 1.5 V, Single-Supply, One-Transistor CMOS EEPROM 一个1.5 V，单电源，单晶体管CMOS EEPROM
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468761
B. Gerber, J. Martin, J. Fellrath
{"title":"A 1.5 V, Single-Supply, One-Transistor CMOS EEPROM","authors":"B. Gerber, J. Martin, J. Fellrath","doi":"10.1109/ESSCIRC.1980.5468761","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468761","url":null,"abstract":"A 1.5 V, single-supply, one-transistor p-ch CMOS EEPROM array has been developed. Negative write and erase voltages of -28V are generated on-chip by voltage multipliers and fed by a 1.5 V logic to the matrix array. Erase and writing times are 25 ms. Endurance is 104-105 cycles.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115155156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An 18K Bipolar Dynamic Random Access Memory Chip 一种18K双极动态随机存取存储器芯片
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468765
R. F. Penoyer, B. El Kareh, R. Houghton, P. Lane, T. A. Selfridge
{"title":"An 18K Bipolar Dynamic Random Access Memory Chip","authors":"R. F. Penoyer, B. El Kareh, R. Houghton, P. Lane, T. A. Selfridge","doi":"10.1109/ESSCIRC.1980.5468765","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468765","url":null,"abstract":"A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127082290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A New IC for Chroma Decoder Stage in TV Receiver 一种用于电视接收机色度解码级的新型集成电路
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468744
M. Van Den Driessche, F. Van Zanten, D. Wojerz
{"title":"A New IC for Chroma Decoder Stage in TV Receiver","authors":"M. Van Den Driessche, F. Van Zanten, D. Wojerz","doi":"10.1109/ESSCIRC.1980.5468744","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468744","url":null,"abstract":"A new integrated chroma decoder has been designed in order to fill the need of a high performance compact SECAM decoder in TV receivers with essentially no trimming, and a low number of external components. The functions of this circuit are described on the following sections.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125977824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Impact of Semiconductor Large-Scale Integration on Telecommunications 半导体大规模集成化对电信的影响
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468796
K. Gerlach
{"title":"The Impact of Semiconductor Large-Scale Integration on Telecommunications","authors":"K. Gerlach","doi":"10.1109/ESSCIRC.1980.5468796","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468796","url":null,"abstract":"This paper gives an overview of the various improvements in world-wide telecommunications, either at the planning stage or already under development, that are realisable as a direct result of semiconductor LSI advances. The particular demands on these circuits and various problems arising during their development are discussed.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127482460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computer-Simulation of Nonlinear GaAs MESFET Circuits 非线性GaAs MESFET电路的计算机模拟
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468758
C. Azizi, J. Kamdem, J. Graffeuil, P. Rossel
{"title":"Computer-Simulation of Nonlinear GaAs MESFET Circuits","authors":"C. Azizi, J. Kamdem, J. Graffeuil, P. Rossel","doi":"10.1109/ESSCIRC.1980.5468758","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468758","url":null,"abstract":"From a computer-aided circuits analysis program, the nonlinear analysis of microwave GaAs field-effect transistors amplifier and the performance and the limitation of Normally-ON Logic gates using MESFET's are described.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128328589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of components development on telecommunication - systems 组件发展对电信系统的影响
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468722
J. Picquendar
{"title":"Influence of components development on telecommunication - systems","authors":"J. Picquendar","doi":"10.1109/ESSCIRC.1980.5468722","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468722","url":null,"abstract":"In this paper, the author will try to show you which type of electronic components LSI circuits particularly the telecommunications industry will need in the eighties. Choices still will have to be made between possible solutions to different problems. But, as the aims become clear and certain, the needs of new components become more precise.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121112067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Unity Gain Buffer and its Implementation in Sampled-Analog Delay Lines CMOS单位增益缓冲器及其在采样模拟延迟线上的实现
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468784
A. Lagos, C. Chan
{"title":"A CMOS Unity Gain Buffer and its Implementation in Sampled-Analog Delay Lines","authors":"A. Lagos, C. Chan","doi":"10.1109/ESSCIRC.1980.5468784","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468784","url":null,"abstract":"The operation of a CMOS unity gain buffer and its implementation in short analog delay lines are discussed, A functional second-order circuit has been successfully realized using an integrated three-stage delay line.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121472905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
MOSAIC: A Design Methodology for VLSI Custom Circuits 马赛克:VLSI定制电路的设计方法
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468718
J. M. C. A. Marques
{"title":"MOSAIC: A Design Methodology for VLSI Custom Circuits","authors":"J. M. C. A. Marques","doi":"10.1109/ESSCIRC.1980.5468718","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468718","url":null,"abstract":"In this paper a design methodology for very complex custom circuits (more than 100 000 MOS) is presented. This method is based on a multiprocessor architecture assembled from a library of modules (functional processors) interconnected by a communication kernel based on a hardware implementation of the software monitor concept.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133382396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Injection Coupled Shift Registers and Counters 注入耦合移位寄存器和计数器
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468772
N. Friedman, C. Salama, P. Thompson
{"title":"Injection Coupled Shift Registers and Counters","authors":"N. Friedman, C. Salama, P. Thompson","doi":"10.1109/ESSCIRC.1980.5468772","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468772","url":null,"abstract":"Novel synchronous shift registers and counters with on-chip clock generators using a modified I2L injector structure are presented. The circuits exhibit a significant increase in functional density and an excellent power-delay-area product.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"15 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130082508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An NMOS Dual Mode Low-Pass Filter for Colour T.V. 彩色电视用NMOS双模低通滤波器
ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI: 10.1109/ESSCIRC.1980.5468748
H. Veendrick
{"title":"An NMOS Dual Mode Low-Pass Filter for Colour T.V.","authors":"H. Veendrick","doi":"10.1109/ESSCIRC.1980.5468748","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468748","url":null,"abstract":"Digital television requires several building blocks to perform the total video signal processing digitally. One of them is a chroma filter, which has to separate the colour information from the brightness information (luminance). In this paper two 17.7 MHz digital low-pass filters are discussed, which perform-in combination with other circuitry-the above mentioned function. Both filter functions are implemented in a dual mode chip made in 4/um NMOS E/D technology with implanted undercrossings.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123350535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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