An 18K Bipolar Dynamic Random Access Memory Chip

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468765

R. F. Penoyer, B. El Kareh, R. Houghton, P. Lane, T. A. Selfridge

引用次数: 1

Abstract

A 2K × 9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75ns and 300ns access and cycle time, respectively. The design is based on a two device cell of 800μm size and all chip input and output signals are TTL compatible.

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一种18K双极动态随机存取存储器芯片

介绍了一种2K × 9双极动态随机存取存储器(RAM)实验芯片，其存取时间和周期分别为75ns和300ns。该设计基于800μm大小的两个器件单元，所有芯片输入和输出信号都是TTL兼容的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC 80: 6th European Solid State Circuits Conference

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