2016 12th European Dependable Computing Conference (EDCC)最新文献

Assuring Dependable Cloud-Based System Engineering: A Cloud Accountability Method 确保可靠的基于云的系统工程:一种云问责方法

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-12-12 DOI: 10.1109/EDCC.2016.20

D. Adjepon-Yamoah, Z. Wen

{"title":"Assuring Dependable Cloud-Based System Engineering: A Cloud Accountability Method","authors":"D. Adjepon-Yamoah, Z. Wen","doi":"10.1109/EDCC.2016.20","DOIUrl":"https://doi.org/10.1109/EDCC.2016.20","url":null,"abstract":"This work introduces a methodology for cloud accountability that assures system dependability in terms of availability and reliability. This assurance is provided relative to the cloud service level agreement. The presented methodology is guided by the NIST SP800-86 digital forensic model, that motivates the collection, examination and analysis of data from the cloud platform, and the generated evidence including logs and context are reported to appropriate cloud agents. As part of this work, we present a novel approach to collecting digital evidence to support cloud-based system dependability, using the Virtual Machine Introspection (VMI) technique. Our VMI approach complements, as well as checks the dependability metrics provided by the cloud service providers (CSPs) as evidence. This methodology, including the VMI approach is particularly relevant since it provides a means of addressing the perceived lack of trust for cloud-based services towards cloud accountability. Our research focuses on applying an evidence-based methodology - cloud accountability method - to cloud-based system engineering for assuring cloud agents of the dependability of cloud platforms.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121697828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Diversity, Safety and Security in Embedded Systems: Modelling Adversary Effort and Supply Chain Risks 嵌入式系统的多样性，安全性和安全性:模拟对手的努力和供应链风险

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-12-12 DOI: 10.1109/EDCC.2016.27

Ilir Gashi, A. Povyakalo, L. Strigini

{"title":"Diversity, Safety and Security in Embedded Systems: Modelling Adversary Effort and Supply Chain Risks","authors":"Ilir Gashi, A. Povyakalo, L. Strigini","doi":"10.1109/EDCC.2016.27","DOIUrl":"https://doi.org/10.1109/EDCC.2016.27","url":null,"abstract":"We present quantitative considerations for the design of redundancy and diversity in embedded systems with security requirements. The potential for malicious activity against these systems have complicated requirements and design choices. New design trade-offs have arisen besides those already familiar in this area: for instance, adding redundancy may increase the attack surface of a system and thus increase overall risk. Our case study concerns protecting redundant communications between a control system and its controlled physical system. We study the effects of using: (i) different encryption keys on replicated channels, and (ii) diverse encryption schemes and implementations. We consider two attack scenarios, with adversaries having access to (i) ways of reducing the search space in attacks using random searches for keys; or (ii) hidden major flaws in some crypto algorithm or implementation. Trade-offs between the requirements of integrity and confidentiality are found, but not in all cases. Simple models give useful design insights. In this system, we find that key diversity improves integrity without impairing confidentiality - no trade-offs arise between the two - and it can substantially increase adversary effort, but it will not remedy substantial weaknesses of the crypto system. Implementation diversity does involve design trade-offs between integrity and confidentiality, which we analyse, but turns out to be generally desirable for highly critical applications of the control system considered.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122528513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches 研究进程变化和系统工作负载对STT-RAM缓存可靠性的影响

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.10

Elham Cheshmikhani, Amir Mahdi Hosseini Monazzah, Hamed Farbeh, S. Miremadi

{"title":"Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches","authors":"Elham Cheshmikhani, Amir Mahdi Hosseini Monazzah, Hamed Farbeh, S. Miremadi","doi":"10.1109/EDCC.2016.10","DOIUrl":"https://doi.org/10.1109/EDCC.2016.10","url":null,"abstract":"In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only by workload behaviors, but also by process variations. Several studies characterized the reliability of STTRAM caches just for one cell, but vulnerability of STT-RAM caches cannot be directly derived from these models. This paper extrapolates the reliability characteristics of one STTRAM cell presented in previous studies to the vulnerability analysis of STT-RAM caches. To this end, we propose a highlevel framework to investigate the vulnerability of STT-RAM caches affected by the per-cell disturbance/failure rates as well as the workloads behaviors and process variations. This framework is an augmentation of gem5 simulator. The investigation reveals that: 1) the read disturbance rate in a cache varies by 6 orders of magnitude for different workloads, 2) the write failure rate varies by 4 orders of magnitude for different workloads, and 3) the process variations increase the read disturbance and write failure rates by up to 5.8x and 8.9x, respectively.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116699468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

3D-DPS: An Efficient 3D-CAC for Reliable Data Transfer in 3D ICs 3D- dps: 3D ic中可靠数据传输的高效3D- cac

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.23

Z. Shirmohammadi, Nezam Rohbani, S. Miremadi

{"title":"3D-DPS: An Efficient 3D-CAC for Reliable Data Transfer in 3D ICs","authors":"Z. Shirmohammadi, Nezam Rohbani, S. Miremadi","doi":"10.1109/EDCC.2016.23","DOIUrl":"https://doi.org/10.1109/EDCC.2016.23","url":null,"abstract":"Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on TSVs. The severity of TSV-to-TSV crosstalk faults depend on the transition patterns appearing on the TSVs. To reduce the crosstalk faults in TSVs, this paper intends to propose Fibonacci-based 3D-Crosstalk Avoidance Code (3D-CAC) called 3D-Doubled Penultimate Summation-based (3D-DPS) CAC. 3D-DPS can completely omit 3D-Tripple opposite Direction Transition (3D-TOD) and is applicable to any arbitrary width of 3×N TSV mesh. 3D-DPS has not ambiguity in representing code words and generates unique code word for each data word. In addition, 3D-DPS considers overlaps between transitions of 3×N TSV meshs by using a mechanism called Coding Window. Evaluation results show that 3D-DPS reduces the area occupation, power consumption and critical path of codec by 53.0%, 25.2% and 1.5%, respectively in comparison with state-of-the-art 3D-CAC.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Software Metrics and Security Vulnerabilities: Dataset and Exploratory Study 软件度量和安全漏洞:数据集和探索性研究

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.34

Henrique Alves, B. Neto, Nuno Antunes

{"title":"Software Metrics and Security Vulnerabilities: Dataset and Exploratory Study","authors":"Henrique Alves, B. Neto, Nuno Antunes","doi":"10.1109/EDCC.2016.34","DOIUrl":"https://doi.org/10.1109/EDCC.2016.34","url":null,"abstract":"Code with certain characteristics is more prone to have security vulnerabilities. In fact, studies show that code not following best practices is harder to verify and maintain, and consequently is more probable to have vulnerabilities left unnoticed or inadvertently introduced. In this experience report, we study whether software metrics can reflect such characteristics, thus having some correlation with the existence of vulnerabilities. The analysis is based on 2875 security patches, used to build a dataset with metrics and vulnerabilities for all the functions, classes and files of 5750 versions of five widely used projects that are exposed to attacks: Linux Kernel, Mozilla, Xen Hypervisor, httpd and glibc. We calculated software metrics from their sources and used correlation algorithm and statistical tests on these metrics in order to identify relations between them and the existing vulnerabilities. Results show that software metrics are able to discriminate vulnerable and non vulnerable functions, but it is not possible to find strong correlations between these metrics and the number of vulnerabilities existing in the analyzed functions. Finally, the results indicate that vulnerable functions are probable to have other vulnerabilities in the future.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116324314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

Transitioning Fault Prediction Models to a New Environment 故障预测模型在新环境中的转换

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.21

Jesper Derehag, E. Weyuker, T. Ostrand, Daniel Sundmark

引用次数: 3

On the Effects of Cumulative SEUs in FPGA-Based Systems 基于fpga的系统中累积seu的影响

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.31

J. Nunes, J. Cunha, M. Z. Rela

{"title":"On the Effects of Cumulative SEUs in FPGA-Based Systems","authors":"J. Nunes, J. Cunha, M. Z. Rela","doi":"10.1109/EDCC.2016.31","DOIUrl":"https://doi.org/10.1109/EDCC.2016.31","url":null,"abstract":"Field programmable hardware, namely FPGA, is increasingly being used in critical applications. These state-of-the-art devices are based on SRAM memory, which is very sensitive to faults. However, due to the characteristics of such devices, errors on memory cells usually have no immediate effect on the implemented system's outputs, meaning that they can be either harmless or eventually cause a late system failure due to a long latency. This is the reason why some manufacturers, such as Xilinx, added a scrubbing capability to some FPGAs, allowing the designers to periodically reprogram the memory cells, wiping any latent error. In this paper we investigate how useful could this scrubbing be, by measuring the error latencies in SRAM memory cells affecting a PID-based cruise control system. Errors are emulated through fault injection using the Fault Injector for Reconfigurable Embedded Devices - FIRED, through Partial Dynamic Reconfiguration. The results show that about half of the system failures were due to errors with long latencies, which could be avoided by reprogramming the FPGA. We have also observed an interesting phenomenon: some failures are due to the combination of faults that, taken in isolation, would have been innocuous to the system.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127180604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Performance Comparison of Algorithms for Byzantine Agreement in Distributed Systems 分布式系统中拜占庭协议算法的性能比较

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.17

Shreya Agrawal, Khuzaima S. Daudjee

{"title":"A Performance Comparison of Algorithms for Byzantine Agreement in Distributed Systems","authors":"Shreya Agrawal, Khuzaima S. Daudjee","doi":"10.1109/EDCC.2016.17","DOIUrl":"https://doi.org/10.1109/EDCC.2016.17","url":null,"abstract":"Reaching agreement in the presence of byzantine processes is an important task in distributed systems. Theoretical analysis of algorithms for Byzantine Agreement can provide insight into their efficiency. However, analysis of algorithms under varying parameters and practical constraints through experimental evaluation can be key to understanding the performance and trade-offs of theoretically well-performing algorithms. We compare the performance of two randomized byzantine agreement algorithms-one using the pull-push approach and another using the concept of quorums-and a third recent simple deterministic byzantine agreement algorithm. Through implementation on a testbed environment using the metrics of bit complexity, round complexity and latency in the presence of network sizes and faulty processes, we quantify the performance of each algorithm. In terms of bit complexity, we show that for small networks (n <; 32) and up to 10% faulty processes, the simple deterministic algorithm performs best, while for larger networks, pull-push is the best performing algorithm. The second randomized algorithm performs best in terms of latency.","PeriodicalId":166039,"journal":{"name":"2016 12th European Dependable Computing Conference (EDCC)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122459788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Inferring a Distributed Application Behavior Model for Anomaly Based Intrusion Detection 基于异常的入侵检测分布式应用行为模型的推导

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.13

Eric Totel, Mouna Hkimi, M. Hurfin, M. Leslous, Y. Labiche

引用次数: 9

Towards a Common Safety Ontology for Automobiles and Railway Vehicles 面向汽车和轨道车辆的通用安全本体

2016 12th European Dependable Computing Conference (EDCC) Pub Date : 2016-09-01 DOI: 10.1109/EDCC.2016.15

B. Hulin, H. Kaindl, Thomas Rathfux, R. Popp, Edin Arnautovic, Roland Beckert

引用次数: 7