2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)最新文献_第2页

Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization 基于边界条件自适应标化的电动汽车EES系统尺寸与配置

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6659013

Wanli Chang, M. Lukasiewycz, S. Steinhorst, S. Chakraborty

{"title":"Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization","authors":"Wanli Chang, M. Lukasiewycz, S. Steinhorst, S. Chakraborty","doi":"10.1109/CODES-ISSS.2013.6659013","DOIUrl":"https://doi.org/10.1109/CODES-ISSS.2013.6659013","url":null,"abstract":"Electric vehicles (EVs) are widely considered as a solution for efficient, sustainable and intelligent transportation. An electrical energy storage (EES) system is the most important component in an EV in terms of performances and cost. This work proposes an approach for optimal dimensioning and configuration of EES systems in EVs. It is challenging to find optimal design points in the parameter space, which expands exponentially with the number of battery types available and the number of cells that can be implemented for each type. A multi-objective optimization problem is formulated with the driving range, rated power output, installation space and cost as design targets. We report a novel boundary-conditioned adaptive scalarization technique to solve both convex and concave problems. It provides a Pareto surface of evenly distributed Pareto points, presents the group of Pareto points according to different specific requirements from automotive manufacturers and also takes the fact in EES system design into account that the importance of an objective could be nonlinear to its value. Numerical and practical experiments prove that our proposed approach is effective for industry use and produces optimal solutions.","PeriodicalId":163484,"journal":{"name":"2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115676475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs WHISK:异构嵌入式soc中动态信息流跟踪的非核心架构

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6658991

J. Porquet, S. Sethumadhavan

引用次数: 18

pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment pvFPGA:在半虚拟化环境中访问基于fpga的硬件加速器

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6658997

Wei Wang, M. Bolic, J. Parri

{"title":"pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment","authors":"Wei Wang, M. Bolic, J. Parri","doi":"10.1109/CODES-ISSS.2013.6658997","DOIUrl":"https://doi.org/10.1109/CODES-ISSS.2013.6658997","url":null,"abstract":"In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time.","PeriodicalId":163484,"journal":{"name":"2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134343782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 62

Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor 基于VectorBlox MXP矩阵处理器的fpga嵌入式超级计算

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6658993

Aaron Severance, G. Lemieux

引用次数: 64

Automatic refinement of requirements for verification throughout the SoC design flow 在整个SoC设计流程中自动细化验证需求

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6659016

L. Pierre, Zeineb Bel Hadj Amor

{"title":"Automatic refinement of requirements for verification throughout the SoC design flow","authors":"L. Pierre, Zeineb Bel Hadj Amor","doi":"10.1109/CODES-ISSS.2013.6659016","DOIUrl":"https://doi.org/10.1109/CODES-ISSS.2013.6659016","url":null,"abstract":"This paper focuses on the verification of requirements for hardware/software systems on chip (SoC's) along the design flow. In the early stages of this flow, the Electronic System Level (ESL) description style, and languages such as SystemC TLM, enable high-level debugging of the SoC functionality. In the last stages, hardware blocks become RTL or gate level (VHDL or Verilog) descriptions. We have developed two autonomous Assertion-Based Verification (ABV) solutions, for SystemC TLM platforms and for VHDL/Verilog IP blocks: designs are automatically instrumented with ad hoc property checkers produced from requirements formalized as PSL assertions. Furthermore, for a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions into their counterparts at the RT level. This paper discusses this issue and proposes a first set of transformation rules for the automatic refinement of PSL assertions from the system level to the signal level. Properties of an industrial case study are used as illustrative examples.","PeriodicalId":163484,"journal":{"name":"2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129822014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems 云系统的能源和截止日期感知资源配置，调度和优化框架

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6659018

Yue Gao, Yanzhi Wang, S. Gupta, Massoud Pedram

{"title":"An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems","authors":"Yue Gao, Yanzhi Wang, S. Gupta, Massoud Pedram","doi":"10.1109/CODES-ISSS.2013.6659018","DOIUrl":"https://doi.org/10.1109/CODES-ISSS.2013.6659018","url":null,"abstract":"Cloud computing has attracted significant attention due to the increasing demand for low-cost, high performance, and energy-efficient computing. Profit maximization for the cloud service provider (CSP) is a key objective in the large-scale, heterogeneous, and multi-user environment of a cloud system. This paper addresses the problem of minimizing the operation cost of a cloud system by maximizing its energy efficiency while ensuring that user deadlines as defined in Service Level Agreements are met. The workload in the cloud system can be modeled as independent batch requests or as task graphs with dependencies. This paper adopts the latter modeling approach, which provides more opportunities for energy and performance optimizations, thus enabling the CSP to meet user deadlines at lower operation costs. However, these optimizations require additional supporting efforts e.g., resource provisioning, virtual machine placement, and task scheduling, which are addressed in a holistic manner in the proposed framework. In the envisioned cloud environment, users can construct their own services and applications based on the available set of virtual machines, but are relieved from the burden of resource provisioning and task scheduling. The CSP will then exploit data parallelism in user workloads to create an energy and deadline-aware cloud platform.","PeriodicalId":163484,"journal":{"name":"2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 87

Embedded neuromorphic vision systems 嵌入式神经形态视觉系统

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6659009

K. Irick

引用次数: 0

Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet 改进了以太网加权轮询调度的最坏情况时间分析

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6659012

Daniel Thiele, Jonas Diemer, Philip Axer, R. Ernst, Jan R. Seyler

引用次数: 21

VarEMU: An emulation testbed for variability-aware software VarEMU:可变性感知软件的仿真测试平台

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6659014

L. Wanner, Salma Elmalaki, Liangzhen Lai, Puneet Gupta, M. Srivastava

{"title":"VarEMU: An emulation testbed for variability-aware software","authors":"L. Wanner, Salma Elmalaki, Liangzhen Lai, Puneet Gupta, M. Srivastava","doi":"10.1109/CODES-ISSS.2013.6659014","DOIUrl":"https://doi.org/10.1109/CODES-ISSS.2013.6659014","url":null,"abstract":"Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications.","PeriodicalId":163484,"journal":{"name":"2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"372 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache 在DRAM缓存中使用自适应银行映射策略减少核间缓存争用

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2013-09-29 DOI: 10.1109/CODES-ISSS.2013.6658988

F. Hameed, L. Bauer, J. Henkel

引用次数: 8