2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献

A thermal stress-aware algorithm for power and temperature management of MPSoCs 一种用于mpsoc电源和温度管理的热应力感知算法

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0761

M. Kamal, Arman Iranfar, A. Afzali-Kusha, M. Pedram

{"title":"A thermal stress-aware algorithm for power and temperature management of MPSoCs","authors":"M. Kamal, Arman Iranfar, A. Afzali-Kusha, M. Pedram","doi":"10.7873/DATE.2015.0761","DOIUrl":"https://doi.org/10.7873/DATE.2015.0761","url":null,"abstract":"In this work, we propose a thermal stress-aware algorithm for the management of the power and temperature in MPSoCs. The algorithm, which uses a heuristic approach, controls the power consumption, maximum temperature, thermal cycles, and temporal/spatial thermal gradients of MPSoCs. At the top level, the decision on turning the cores on and off is made based on the constraints of peak temperature, maximum spatial thermal gradient, and power consumption. At the next tier, the optimal frequencies (and supply voltages) of the ON cores, formulated in a convex optimization problem, are determined again based on satisfying the constraints of the maximum total power consumption, peak temperature, thermal cycles, and also temporal thermal gradient. The technique may be applied to both the heterogeneous and homogenous MPSoCs. The efficacy of the proposed approach in reducing the thermal cycles as well as temporal thermal gradient is evaluated by comparing its results with a similar previous power and temperature management approach. The evaluation which is performed on 8-core processors under Splash2 benchmarks, demonstrates the ability of the suggested technique in limiting a considerable reduction in the thermal stress parameters.","PeriodicalId":162450,"journal":{"name":"2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127191453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Timing analysis of an avionics case study on complex hardware/software platforms 基于复杂硬件/软件平台的航电案例时序分析

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0189

Franck Wartel, Leonidas Kosmidis, A. Gogonel, Andrea Baldovin, Z. Stephenson, B. Triquet, E. Quiñones, Code Lo, E. Mezzetti, I. Broster, J. Abella, L. Cucu-Grosjean, T. Vardanega, F. Cazorla

{"title":"Timing analysis of an avionics case study on complex hardware/software platforms","authors":"Franck Wartel, Leonidas Kosmidis, A. Gogonel, Andrea Baldovin, Z. Stephenson, B. Triquet, E. Quiñones, Code Lo, E. Mezzetti, I. Broster, J. Abella, L. Cucu-Grosjean, T. Vardanega, F. Cazorla","doi":"10.7873/DATE.2015.0189","DOIUrl":"https://doi.org/10.7873/DATE.2015.0189","url":null,"abstract":"Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular have been shown to facilitate the estimation of the worst-case execution time (WCET). MBPTA relies on specific hardware and software support to randomise and/or upper bound a number of sources of execution time variation to drastically reduce the need for user-provided information, thus replacing uncertainty by probabilities. MBPTA has been proven effective for specific single-core processor designs. However, particular hardware features and multicores in general challenge MBPTA application in industrial-quality developments. While solutions to those challenges have been proven on benchmarks, they have not been proven yet on real-world applications, whose timing analysis is far more challenging than that of simple benchmarks. This paper discusses the application of MBPTA to a real avionics system in the context of (1) software-only single-core solutions and (2) hardware-only multicore solutions with an ARINC 653 operating system.","PeriodicalId":162450,"journal":{"name":"2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51

Automated rectification methodologies to functional state-space unreachability 功能状态空间不可达性的自动纠正方法

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.5555/2755753.2757138

Ryan Berryhill, A. Veneris

引用次数: 10

NFRs early estimation through software metrics 通过软件度量对nfr进行早期评估

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0877

A. Vieira, Pedro Faustini, L. Carro, É. Cota

引用次数: 1

Minimizing the number of process corner simulations during design verification 在设计验证过程中尽量减少工艺拐角模拟的次数

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0970

Michael Shoniker, B. Cockburn, Jie Han, W. Pedrycz

引用次数: 8

Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration 协同使用多个片上网络，实现超低延迟和可扩展的分布式路由重新配置

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0392

Marco Balboni, J. Flich, D. Bertozzi

引用次数: 11

Feature selection for Alternate Test using wrappers: Application to an RF LNA case study 使用包装器的替代测试的特征选择:应用于RF LNA案例研究

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0179

M. Barragán, G. Léger

引用次数: 3

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs CGRAs上嵌套循环映射的联合仿射变换和循环流水线

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0713

S. Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo

引用次数: 4

FP-scheduling for mode-controlled dataflow: A case study 模式控制数据流的fp调度:一个案例研究

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0938

Alok Lele, Orlando Moreira, K. V. Berkel

引用次数: 10

Sub-10 nm FinFETs and tunnel-FETs: From devices to systems 10纳米以下的fet和隧道fet:从器件到系统

2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2015-03-09 DOI: 10.7873/DATE.2015.0870

Ankit Sharma, A. A. Goud, K. Roy

{"title":"Sub-10 nm FinFETs and tunnel-FETs: From devices to systems","authors":"Ankit Sharma, A. A. Goud, K. Roy","doi":"10.7873/DATE.2015.0870","DOIUrl":"https://doi.org/10.7873/DATE.2015.0870","url":null,"abstract":"In this paper, a detailed device/circuit/system level assessment of sub-10nm GaSb-InAs Tunneling Field Effect Transistors (TFET) versus Silicon FinFETs operating at near-threshold voltages is reported. A source underlapped GaSb-InAs TFET is used to achieve lower subthreshold swings than previously reported TFETs and an analytical justification is provided to explain the observed improvement. Through atomistic, 2D ballistic simulations using self-consistently, coupled Non-equilibrium Green's Function (NEGF)-Poisson approach, GaSb-InAs TFET and Silicon FinFET device characteristics are derived from which compact models are extracted for SPICE simulations. Circuit simulations of a 6-stage inverter chain show that sub-10nm underlapped TFETs are especially suited for near-threshold computing because of their ability to achieve higher throughput while consuming ~100x lower power compared to Si FinFETs. To analyze the suitability of sub-10 nm TFETs for medium-throughput and ultra-low power applications in future very large scale integrated designs, a LEON3 processor is synthesized at VDD=0.25V. The impact of interconnect parasitics on the performance of TFETs is considered by studying the power-performance of the LEON3 under varying wire-load conditions. Under moderate interconnect parasitics, TFETs-based processor is shown to exhibit more than 50% power reduction compared to FinFETs.","PeriodicalId":162450,"journal":{"name":"2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128232279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8