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Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)最新文献

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Comparison between PVM on RHODOS and Unix 在RHODOS和Unix上PVM的比较
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778931
J. Rough, A. Goscinski
{"title":"Comparison between PVM on RHODOS and Unix","authors":"J. Rough, A. Goscinski","doi":"10.1109/ISPAN.1999.778931","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778931","url":null,"abstract":"Presents the architecture, services and performance results obtained from the implementation of the PVM (Parallel Virtual Machine) parallel processing tool supported by either the Unix operating system or the RHODOS distributed operating system. It is shown that the provision of several advanced services in RHODOS allow the implementation of PVM to be greatly simplified, and significant speed-ups to applications can be achieved. These services allow the dynamic establishment of a virtual machine by removing heavily loaded and adding idle/lightly loaded workstations, placing processes on workstations to optimise static allocation, instantiating processes using group process creation and balancing load dynamically using process migration. The performance study shows that the processing time of PVM applications executed on the RHODOS virtual machine is much shorter than those achieved on the Unix virtual machine.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133897528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fault tolerant processor arrays based on 1 1/2 -track switch with generalized spare distributions 基于广义备用分布的1 1/2磁道开关容错处理器阵列
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778929
T. Horita, I. Takanami
{"title":"Fault tolerant processor arrays based on 1 1/2 -track switch with generalized spare distributions","authors":"T. Horita, I. Takanami","doi":"10.1109/ISPAN.1999.778929","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778929","url":null,"abstract":"As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer-scale integration (WSI) is growing. The major problem for this case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. In this paper, we propose a reconfigurable processor array based on the 1 1/2 -track switch (TS) model, such that spare processing elements (PEs) are not necessarily put around the array, but are more flexibly put in the array by changing the connections of spare PEs to non-spare PEs while retaining the connections among the non-spare PEs in the same manner as those in the 1 1/2 -TS model. The proposed model has a desirable property such that the physical distances between logically adjacent PEs in the reconfigured array are within a constant, i.e. independent of the size of the array. We show that the hardware overhead of the proposed model is a little greater than that of the 1 1/2 -TS model, while the yield of the proposed model is much better than that of the 1 1/2 -TS model.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128159626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance and granularity control in the SPaDES parallel simulation system SPaDES并行仿真系统的性能与粒度控制
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778923
Y. M. Teo, S. Tay
{"title":"Performance and granularity control in the SPaDES parallel simulation system","authors":"Y. M. Teo, S. Tay","doi":"10.1109/ISPAN.1999.778923","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778923","url":null,"abstract":"Parallel simulation has the potential to accelerate the execution of simulation applications. However developing a parallel discrete-event simulation from scratch requires an in-depth knowledge of the mapping process from the physical model to the simulation model, and a substantial effort in optimising performance. This paper presents an overview of the SPaDES (Structured Parallel Discrete-Event Simulation) parallel simulation framework. We focus on the performance analysis of SPaDES/C++, an implementation of SPaDES on a distributed-memory Fujitsu AP3000 parallel computer. SPaDES/C++ hides the underlying complex parallel simulation synchronization and parallel programming details from the simulationist. Our empirical results show that the SPaDES framework can deliver good speedup if the process granularity is properly optimised.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Java4P: Java with high-level concurrency constructs Java4P:具有高级并发性构造的Java
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778960
L. Nugroho, A.S.M. Sajeev
{"title":"Java4P: Java with high-level concurrency constructs","authors":"L. Nugroho, A.S.M. Sajeev","doi":"10.1109/ISPAN.1999.778960","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778960","url":null,"abstract":"While Java has provided a mechanism for concurrent programming implemented as language constructs, it is too rudimentary for most programmers and has certain limitations that make programs unnecessarily complex and prevent fine-grained concurrency. We have implemented Java4P, an extension of the Java language, that offers a simpler concurrency model and overcomes Java's limitations. Threads are no longer associated with thread objects, allowing concurrency at any level of granularity. Thread creation is made implicit and synchronisation is achieved through method guards. Synchronisation specification is separated from the functional specification to provide a parallel programming model closer to sequential programming.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129288831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A scalable and efficient storage allocator on shared-memory multiprocessors 共享内存多处理器上可扩展且高效的存储分配器
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778944
Voon-Yee Vee, W. Hsu
{"title":"A scalable and efficient storage allocator on shared-memory multiprocessors","authors":"Voon-Yee Vee, W. Hsu","doi":"10.1109/ISPAN.1999.778944","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778944","url":null,"abstract":"An efficient dynamic storage allocator is important for time-critical parallel programs. In this paper, we present a fast and simple parallel allocator for fixed size block on shared-memory multiprocessors. We show both theoretically and empirically that the allocator incurs very low lock contention. The allocator is tested with parallel simulation applications with frequent allocation and release requests. The results confirm that our allocator is highly efficient and is scalable to more processors.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131184351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A parallel algorithm for the degree-constrained minimum spanning tree problem using nearest-neighbor chains 基于最近邻链的度约束最小生成树并行算法
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778937
L. Mao, N. Deo, S. Lang
{"title":"A parallel algorithm for the degree-constrained minimum spanning tree problem using nearest-neighbor chains","authors":"L. Mao, N. Deo, S. Lang","doi":"10.1109/ISPAN.1999.778937","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778937","url":null,"abstract":"The Minimum Spanning Tree (MST) problem with an added constraint that no node in the spanning tree has the degree more than a specified integer d, is known as the Degree-Constrained MST (d-MST) problem. Since computing the d-MST is NP-hard for every d in the range 2/spl les/d/spl les/(n-2) where n denotes the total number of nodes, several approximate algorithms have been proposed in the literature. We have previously proposed two approximate algorithms, TC-RNN and IR, for the d-MST problem (L.J. Mao et al., 1997). Our experimental results show that while the IR algorithm is faster, the TC-RNN algorithm consistently produces spanning trees with a smaller weight. We propose a new algorithm, TC-NNC, which is an improved version of TC-RNN. Our experiments using randomly generated, weighted graphs as input, demonstrate that the execution time of TC-NNC is smaller than that of TC-RNN, and is very close to that of IR. Further, the quality-of-solution of TC-NNC is better than that of IR and is very close to that of TC-RNN.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131412779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Location updates and probabilistic tracking algorithms for mobile cellular networks 移动蜂窝网络的位置更新和概率跟踪算法
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778976
John C.S. Lui, C. C. Fong, Horace Wai-kit Chan
{"title":"Location updates and probabilistic tracking algorithms for mobile cellular networks","authors":"John C.S. Lui, C. C. Fong, Horace Wai-kit Chan","doi":"10.1109/ISPAN.1999.778976","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778976","url":null,"abstract":"In this paper, we develop a novel mathematical model to analyze different location update protocols for mobile cellular network. Our model can capture many important features of user movements, such as geographically dependent movement, directional movement and non-exponential distribution of cell dwell times. We propose to use the transient method to predict the location of a mobile user. This method is efficient and, more importantly, able to address the temporal change in the current location of a mobile user. Therefore, the accuracy of the prediction of the location of a user can be enhanced. We also propose a new location update protocol which can attain a lower trading cost and also adapt to different mobility patterns. Transient performance analysis is also carried out and the results are compared with other protocols.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"30 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131805029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Supporting hierarchy and heterogeneous interfaces in multi-hop wireless ad hoc networks 在多跳无线自组织网络中支持分层和异构接口
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778966
J. Broch, D. Maltz, David B. Johnson
{"title":"Supporting hierarchy and heterogeneous interfaces in multi-hop wireless ad hoc networks","authors":"J. Broch, D. Maltz, David B. Johnson","doi":"10.1109/ISPAN.1999.778966","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778966","url":null,"abstract":"Much progress has been made toward solving the problem of routing packets inside an ad hoc network, but there are presently no complete proposals for connecting ad hoc networks together to form larger networks, or for integrating them with wired Internets. We describe a technique that allows a single ad hoc network to span across heterogeneous link layers. Using this technique, we can both integrate ad hoc networks into the hierarchical Internet and support the migration of mobile nodes from the Internet into and out of ad hoc networks via Mobile IP. Taken together, these solutions improve the scalability of flat ad hoc networks by introducing hierarchy, and they enable all nodes participating in the ad hoc network to be reachable from anywhere in the world. We have implemented each of the solutions in a real testbed of 8 nodes using the Dynamic Source Routing (DSR) protocol. Generalizing our solutions, we describe several abstract scenarios and present our ideas for solving them.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132020839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 240
Summation algorithms on constrained reconfigurable meshes 约束可重构网格的求和算法
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778971
A. Matsuura, A. Nagoya
{"title":"Summation algorithms on constrained reconfigurable meshes","authors":"A. Matsuura, A. Nagoya","doi":"10.1109/ISPAN.1999.778971","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778971","url":null,"abstract":"Constrained reconfigurable meshes are one type of parallel computing model which takes the reconfigurability of hardware into account. With these meshes, a practical assumption is given on the communication power such that a signal is propagated through a constant number of processing elements (PEs) say k PEs, at one unit of time. We present algorithms for the fundamental problem of computing the sum of multiple integers. For the problem of summing n binary values, two show an optimal O(n/k)-time algorithm on a constrained reconfigurable mesh of size m/spl times/n, where m=/spl Theta/(log/sup 2/ k/log log k). For the problem of summing n d-bit integers, we present an O((d+/spl radic/dmm)/k) time algorithm on a constrained reconfigurable mesh of size /spl radic/dmn/spl times//spl times//spl radic/dmn.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115996630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Message scheduling on trees under a generalized line-communication model 广义线路通信模型下树上的消息调度
Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99) Pub Date : 1999-06-23 DOI: 10.1109/ISPAN.1999.778910
D. Barth, Mario Valencia-Pabon
{"title":"Message scheduling on trees under a generalized line-communication model","authors":"D. Barth, Mario Valencia-Pabon","doi":"10.1109/ISPAN.1999.778910","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778910","url":null,"abstract":"In this paper, we generalize the line-communication model by relaxing the notion of conflictness between paths. We show that the problem of finding optimal schedules to route any set of messages under both our generalized line-communication model and the bufferless routing model is NP-hard even if restricted to binary trees. Finally, a simple offline 2-approximation algorithm for our model on trees is presented.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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