Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)最新文献

{"title":"An optimal embedding of incomplete binary trees onto incomplete hypercubes","authors":"Chien-Hung Huang, J. Hsiao, Richard C. T. Lee, Jywe-Fei Fang","doi":"10.1109/ISPAN.1999.778921","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778921","url":null,"abstract":"It has been proved that incomplete binary trees can not be embedded onto incomplete hypercubes with both expansion-1 and dilation-1. In this paper we propose an optimal embedding algorithm to embed this issue with expansion-1, dilation-2. Our algorithm is a linear time algorithm, which is optimal in terms of time complexity. Furthermore, the embedding scheme is as desirable to be simple such that the implementation is quite easy.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115422972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance of fault tolerant networks of workstations","authors":"John Morris","doi":"10.1109/ISPAN.1999.778928","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778928","url":null,"abstract":"Functional or dataflow models of computation enable a program's run-time system to determine which portions of a computation must be repeated when faults occur. Straightforward modifications to the run-time system of Cilk 2.0 (a threaded extension of C) enable a network-of-workstations parallel processing system to tolerate fail-stop faults of the individual processors or the network. It is shown in this paper that the overheads needed to provide this fault tolerance are mainly CPU cycles and memory, with very little additional network load being generated in the absence of faults. This makes it feasible to run long computations successfully on the typical networks of workstations found in large organisations, where ownership, control and distribution of the individual processors may be widely distributed.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel approach to fast discrete Hartley transform","authors":"J. Liu, F. Chan, F. K. Lam, H. F. Li","doi":"10.1109/ISPAN.1999.778936","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778936","url":null,"abstract":"The Discrete Hartley transform (DHT) is an important tool in digital signal processing. We propose a novel approach to perform DHT. We transform DHT into a form expressed in discrete moments via a modular mapping and truncating Taylor series expansion and present a completely new formula for computing DHT. We extend the use of our systolic array for fast computation of moments without any multiplications, to one that computes DHT with only a few multiplications and without any evaluations of triangular functions. The multiplication number used in our method is O(Nlog/sub 2/N/log/sub 2/log/sub 2/N) superior to O(Nlog/sub 2/N) in the conventional FDT. The execution time of the systolic array is only O(Nlog/sub 2/N/log/sub 2/log/sub 2/N) for 1-D DHT and O(N/sup k/) for k-D DHT (k/spl ges/2). The systolic array consists of very simple processing elements and hence it implies an easy and potential hardware/VLSI implementation. The approach is also applicable to DHT inverses.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115014267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Geographicailly extended LAN","authors":"Z.L. Hudrikis","doi":"10.1109/ISPAN.1999.778952","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778952","url":null,"abstract":"The functional efficiency of an office is enhanced greatly by a shared computer environment. The shared environment is created through homogeneity in computing equipment and software, and by communication among the equipment. The physical extent of the common environment is set by the reach of the LAN that supports the communications, and is generally accepted as being no more than a building, at most a campus. Yet any enterprise or organization that is spread over multiple cities or even countries would be helped by having a single computer environment that would encompass all its locations, provided only that the geographically dispersed environment would sensibly have no greater latencies in computer to computer interactions than prevail in the single campus environ-ment. By name, a LAN appears to be bound to a local area. However only the shared medium subnet is so restricted. A LAN of bridged shared medium segments, can extend over any distance. Therefore a single computer environment for a geographically dispersed organization is a real possibility. The critical requirement is for permanent links of sufficient bandwidth for connecting the bridged segments. The critical issue is the cost of such links.The bandwidth of bridge links will be sufficient when it is same as, or at least comparable to, the bandwidth of the shared media of the LAN segments. A bandwidth of 10 Mbit/sec must regarded as a minimum requirement. Provision of such links over national and global distances on any exclusive basis will invariably prove prohibitive in cost. The only viable possibility is on a statistically shared basis: The average usage of any bridge link would be minuscule compared to the required peak rate and therefore, given suitable access control arrangements, a 10 Mbit/sec communication channel could be shared by hundreds, perhaps even thousands, of LAN bridge links. A necessary condition on the sharing is that a single link should be able to use the whole channel capacity whenever that link is alone with any traffic at the given time, and the whole fraction 1/n-th of the capacity when at the time there are (n-1) other links with traffic. A further necessary condition is that despite the hundred per cent statistical sharing, there should be no losses of information by, for instance, buffer overflow at multiplexing points.There are few communications schemes in which such full statistical and loss free sharing of bandwidth is possible, and none are as yet in existence. An outstanding instance of a possible scheme is in ATM networking, namely using controlled cell transfer (CCT). Protocol standards for CCT have been advanced in a wider context of Controlled Transfer (CT) capabilities in ITU-T and are ready for adoption. They have not however (as yet) been accepted on the grounds that CT would not provide anything beyond what can be obtained from already standardized capabilities. That CCT could give an economic basis for LANs of un limited geographic exte","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122696376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalability of a load balancing algorithm, and its implementation on an Intel Paragon","authors":"A. Boukerche, Sajal K. Das","doi":"10.1109/ISPAN.1999.778951","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778951","url":null,"abstract":"This paper describes an efficient implementation of a load balancing algorithm based upon a process migration mechanism, and the notion of CPU-queue length which indicates the workload at each processor. The main objective is to reduce the message overhead in conservative simulation. The algorithms were tested on four simulation workload models to study the the scalability of our algorithm on an Intel Paragon multicomputer architecture using 64 processors. A significant decrease in run time and the message overhead associated with the conservative simulation was obtained with the use of the proposed dynamic load balancing algorithm as compared to the use of a static partitioning algorithm.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"620 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122946415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Randomized adaptive routing based on mobile agents","authors":"M. Bui, A. Datta, O. Flauzac, D. Nguyen","doi":"10.1109/ISPAN.1999.778968","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778968","url":null,"abstract":"The mobile agent has been shown to be a convenient, efficient, and robust approach to designing distributed protocols. This paper introduces an adaptive, mobile agent-based routing algorithm. While performing a random walk through the network, mobile agents sense changes in the network state, and trigger the computation of updated values for the routing tables. The randomized moving strategy exerts a negligible and balanced impact on the network resources, both in terms of bandwidth and computation. The memory requirement is very moderate. The correctness of the protocol is proven and its complexity is analyzed.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126992801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the interval routing of chordal rings","authors":"B. Mans","doi":"10.1109/ISPAN.1999.778911","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778911","url":null,"abstract":"The Shortest-Path Interval Routing Scheme is an efficient strategy to code distributed routing algorithms in a compact way. Characterising networks which admit shortest path Strict Interval Routing Scheme using one interval per edge (1-SIRS) is known to be NP-complete. We study 1-SIRS for a popular class of networks, known as chordal rings. We prove that for any chordal ring of degree 4 with a chord of length k(>3), there exists an infinite set of n, such that the chordal ring <1, k>/sub n/ (of size n) does not admit a 1-SIRS, regardless of the node labeling. This gives a negative answer to an open question from C. Gavoille (1997) and extends the characterisation of node labelings which allow a shortest path 1-SIRS in chordal rings. Mainly, we study the natural cyclic node labeling and derive an alternative node labeling using isomorphic properties. First we show that there is an infinite class of chordal rings with chord k of even length that do not have a shortest path 1-SIRS. Second, we show the limitation of the cyclic node labeling and its alternative representation when k is odd. Finally, we conjecture that any chordal ring with shortest path 1-SIRS has a node labeling isomorphic to a chordal ring with a cyclic node labeling.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvements in parallel job scheduling using gang service","authors":"Fabrício A. B. Silva, I. Scherson","doi":"10.1109/ISPAN.1999.778950","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778950","url":null,"abstract":"Gang scheduling has been widely used as a practical solution to the dynamic parallel job scheduling problem. Parallel threads of a single job are scheduled for simultaneous execution on a parallel computer even if the job does not fully utilize all available processors. Non allocated processors go idle for the duration of the time quantum assigned to the threads. In this paper we propose a class of scheduling policies, dubbed concurrent gang, that is a generalization of gang-scheduling, and allows for the flexible simultaneous scheduling of multiple parallel jobs, thus improving the space sharing characteristics of gang scheduling. However all the advantages of gang scheduling such as responsiveness, efficient sharing of resources, ease of programming, etc., are maintained.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127900631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A VLSI architecture for cellular automata based Reed-Solomon decoder","authors":"Sukumar Nandi, C. Rambabu, P. P. Chaudhuri","doi":"10.1109/ISPAN.1999.778933","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778933","url":null,"abstract":"The design of cellular automata (CA)-based SbEC-DbED (single-byte error correcting, double-byte error detecting) code, which is analogous to the extended Reed-Solomon (RS) code, was proposed by D.R. Chowdhury et al. (1994). This code has the same restriction on error correction capability as that of the extended RS code. In this paper, a new scheme has been proposed for pipeline implementation of CA-based tbEC-tbED (t-byte error correcting, t-byte error detecting) codes that are analogous to the conventional RS code. The encoder and decoder of this code can both be implemented in a pipeline with a CA array. The proposed decoder provides a simple, modular and cost-effective design that is ideally suited for VLSI implementation.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault-tolerance using cache-coherent distributed shared memory systems","authors":"D. Hecht, K. Kavi, R. Gaede, C. Katsinis","doi":"10.1109/ISPAN.1999.778924","DOIUrl":"https://doi.org/10.1109/ISPAN.1999.778924","url":null,"abstract":"Describes new protocols augmenting traditional cache coherency mechanisms to implement fault tolerance based on recovery blocks and checkpointing. Concurrent processes compound rollback recovery since the rollback can potentially lead to a \"domino effect\" whereby the process is rolled back to the beginning. Several approaches have been proposed to limit the domino effect. One set of such techniques requires communicating processes to periodically synchronize in order to checkpoint a globally consistent state. These schemes can be implemented more naturally on distributed shared memory systems using synchronization on shared memory. We have developed extensions to well-known cache-coherency methods (e.g. directory-based) for the implementation of checkpointing consistent states.","PeriodicalId":157641,"journal":{"name":"Proceedings Fourth International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'99)","volume":"16 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132502766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}