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Proceedings of the 7th ACM international conference on Computing frontiers最新文献

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A service-based approach for the execution of scientific workflows in grids 在网格中执行科学工作流的基于服务的方法
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787306
A. Bosin, N. Dessì, Madusudhanan Bairappan
{"title":"A service-based approach for the execution of scientific workflows in grids","authors":"A. Bosin, N. Dessì, Madusudhanan Bairappan","doi":"10.1145/1787275.1787306","DOIUrl":"https://doi.org/10.1145/1787275.1787306","url":null,"abstract":"Scientific workflows may be deployed on heterogeneous distributed environments, including Grid resources whose access is not straightforward when it is non compliant with the specific Grid middleware. This paper addresses this complexity and investigates the feasibility of a service oriented approach that takes advantage of the standardized resource access provided by BPEL. The paper proposes specialized Web services, namely BPEL partners, that support the discovering of suitable resources, monitor the execution of each single workflow task in the resource and aggregate results of the execution. Some implementation hints are presented.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121955509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient and scalable barrier synchronization for many-core CMPs 多核cmp的高效可扩展屏障同步
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787289
José L. Abellán, Juan Fernández, M. Acacio
{"title":"Efficient and scalable barrier synchronization for many-core CMPs","authors":"José L. Abellán, Juan Fernández, M. Acacio","doi":"10.1145/1787275.1787289","DOIUrl":"https://doi.org/10.1145/1787275.1787289","url":null,"abstract":"We present in this work a novel hardware-based barrier mechanism for synchronization on many-core CMPs. In particular, we leverage global interconnection lines (G-lines) and S-CSMA technique, which have been used to overcome some limitations of a flow control mechanism (EVC) in the context of Networks-on-Chip, to develop a simple G-lines-based network that operates independently of the main data network in order to carry out barrier synchronizations. Next, we evaluate our approach by running several applications on top of the Sim-PowerCMP performance simulator. Our method only takes 4 cycles to carry out the synchronization once all cores or threads have arrived at the barrier. Hence, we obtain much better performance results than software-based barrier implementations in terms of scalability and efficiency.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130290538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Session details: Fault tolerance and parallel applications 会话细节:容错和并行应用程序
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/3251917
A. Liehr
{"title":"Session details: Fault tolerance and parallel applications","authors":"A. Liehr","doi":"10.1145/3251917","DOIUrl":"https://doi.org/10.1145/3251917","url":null,"abstract":"","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122269315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A communication infrastructure for a million processor machine 用于百万处理器机器的通信基础设施
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787290
A. Brown, S. Furber, J. Reeve, P. Wilson, Mark Zwolinski, J. Chad, L. Plana, D. Lester
{"title":"A communication infrastructure for a million processor machine","authors":"A. Brown, S. Furber, J. Reeve, P. Wilson, Mark Zwolinski, J. Chad, L. Plana, D. Lester","doi":"10.1145/1787275.1787290","DOIUrl":"https://doi.org/10.1145/1787275.1787290","url":null,"abstract":"SpiNNaker (Spiking Neural Network architecture) is a massively parallel computing machine, comprising a million ARM9 cores. These are realised on 50000 chips, 20 cores/chip. While it could be classed as a MIMD machine, there is no unifying bus structure, and there is no attempt to maintain cross-system memory coherence. Inter-core communication is brokered by a fast message-passing system, built in and managed at the hardware level - thus there is an inevitable tension between speed and flexibility. The message passing infrastructure was designed to be fast and have a high bandwidth; a consequence of this design decision is that the effective data payload is only 32 bits/packet. Whilst this is ample for a wide range of applications, when the system is initialising, it is necessary to transport relatively large and sophisticated data structures across the system. This can be slow and cumbersome, and makes some form of internal self-organisation extremely attractive. This is described in outline here.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122389348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a cloud naming framework 云命名框架的设计
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787305
A. Celesti, M. Villari, A. Puliafito
{"title":"Design of a cloud naming framework","authors":"A. Celesti, M. Villari, A. Puliafito","doi":"10.1145/1787275.1787305","DOIUrl":"https://doi.org/10.1145/1787275.1787305","url":null,"abstract":"In cloud computing environments, naming and resource location become critical issues. Exploiting the concept of resource virtualization, a cloud offers a variety of entities which can be moved from a place to another, needing to be identified with one or more names and logical representations in various contexts. In such scenario, the management of cloud name spaces may become very difficult. This paper proposes a Cloud Naming System Framework (CNSF) able to: I) integrate independent cloud name spaces in federated scenario, II) support the \"mounting\" of names from a cloud name space to another, III) interact with other URI-based naming systems.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134279851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Variant-based competitive parallel execution of sequential programs 基于变量的顺序程序竞争并行执行
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787325
Oliver Trachsel, T. Gross
{"title":"Variant-based competitive parallel execution of sequential programs","authors":"Oliver Trachsel, T. Gross","doi":"10.1145/1787275.1787325","DOIUrl":"https://doi.org/10.1145/1787275.1787325","url":null,"abstract":"Competitive parallel execution (CPE) is a simple yet attractive technique to improve the performance of sequential programs on multi-core and multi-processor systems. A sequential program is transformed into a CPE-enabled program by introducing multiple variants for parts of the program. The performance of different variants depends on runtime conditions, such as program input or the execution platform, and the execution time of a CPE-enabled program is the sum of the shortest variants. Variants compete at run-time under the control of a CPE-aware run-time system. The run-time system ensures that the behavior and outcome of a CPE-enabled program is not distinguishable from the one of its original sequential counterpart. We present and evaluate a run-time system that is implemented as a user-space library and that closely interacts with the operating system. The paper discusses two strategies for the generation of variants and investigates the applicability of CPE for two usage scenarios: i) computation-driven CPE: a simple and straightforward parallelization of heuristic algorithms, and ii) compiler-driven CPE: generation of CPE-enabled programs as part of the compilation process using different optimization strategies. Using a state-of-the-art SAT solver as an illustrative example, we report for compiler-based CPE speedups of 4-6% for many data sets, with a maximum slowdown of 2%. Computation-driven CPE provides super-linear speedups for 5 out of 31 data sets (with a maximum speedup of 7.4) and at most a slow-down of 1% for two data sets.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114873169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Programmable matter with self-reconfiguring robots 可编程物质与自我重新配置的机器人
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787284
D. Rus
{"title":"Programmable matter with self-reconfiguring robots","authors":"D. Rus","doi":"10.1145/1787275.1787284","DOIUrl":"https://doi.org/10.1145/1787275.1787284","url":null,"abstract":"Programmable matter aims to bring machines and materials closer together. We wish to create smart materials whose properties can be programmed, or, alternatively, machines that look and feel more like materials. Programmable matter will be achieved when we will have the ability to create objects whose physical properties, for example shape, stiffness, optical characteristics, acoustic characteristics, and viscosity can be programmed. We are working toward creating materials with embedded sensing, actuation, communication, computation, and connection, which we call SAC3 materials. We are developing two concepts: smart SAC3 sheets that self-fold into origami shapes, and smart SAC3 pebbles that self-sculpt into desired objects. This work is at the intersection of theory, algorithms, device design, and control. This talk will survey the history of programmable matter. We start by discussing robotic self-reconfiguration whose aim is to create modular robots capable of changing shape: hundreds of small modules autonomously organize and reorganize as geometric structures to best fit the terrain on which the robot has to move, the shape of the object the robot has to manipulate, or the sensing needs of the given task. Self-reconfiguration leads to versatile robots that can support multiple modalities of locomotion, manipulation, and perception. We will discuss a spectrum of mechanical and computational capabilities for such systems and detail some recent self-reconfiguring robots. We then discuss programmable matter by smart sheets and smart pebbles. Finally, we discuss the theoretical and systems challenges for realizing the full potential of programmable matter.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122123057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Augmenting cache partitioning with thread-aware insertion/promotion policies to manage shared caches 使用线程感知的插入/提升策略来扩展缓存分区，以管理共享缓存
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787292
Xiufeng Sui, Junmin Wu, Guoliang Chen, Yixuan Tang, Xiaodong Zhu
{"title":"Augmenting cache partitioning with thread-aware insertion/promotion policies to manage shared caches","authors":"Xiufeng Sui, Junmin Wu, Guoliang Chen, Yixuan Tang, Xiaodong Zhu","doi":"10.1145/1787275.1787292","DOIUrl":"https://doi.org/10.1145/1787275.1787292","url":null,"abstract":"In this paper, we augment traditional cache partitioning with thread-aware adaptive insertion and promotion policies to manage shared L2 caches. The proposed mechanism can mitigate destructive inter-thread interference, and meanwhile retain some fraction of the working set in the cache, therefore results in better performance.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129586023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Performance and power evaluation of an in-line accelerator 一种直列加速器的性能与功率评估
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787293
Alejandro Rico, J. Derby, R. Montoye, T. Heil, Chen-Yong Cher, P. Bose
{"title":"Performance and power evaluation of an in-line accelerator","authors":"Alejandro Rico, J. Derby, R. Montoye, T. Heil, Chen-Yong Cher, P. Bose","doi":"10.1145/1787275.1787293","DOIUrl":"https://doi.org/10.1145/1787275.1787293","url":null,"abstract":"In this paper we evaluate the performance and power of a processor-attached in-line accelerator. The accelerator provides high-performance SIMD computing and power efficiency by means of a very large register file and a set of vector multimedia extensions based on IBM's PowerPC VMX. Our experiments show significant performance improvements and power reduction, compared to a baseline vector execution unit, mainly due to the drastic decrease of memory accesses caused by the software-managed locality of the very large register file. Total execution time is, on average, reduced by 61%, while consuming 55% less energy.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130226317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Exploitation of nested thread-level speculative parallelism on multi-core systems 在多核系统上利用嵌套线程级推测并行性
Proceedings of the 7th ACM international conference on Computing frontiers Pub Date : 2010-05-17 DOI: 10.1145/1787275.1787302
A. Kejariwal, M. Girkar, Xinmin Tian, Hideki Saito, A. Nicolau, A. Veidenbaum, U. Banerjee, C. Polychronopoulos
{"title":"Exploitation of nested thread-level speculative parallelism on multi-core systems","authors":"A. Kejariwal, M. Girkar, Xinmin Tian, Hideki Saito, A. Nicolau, A. Veidenbaum, U. Banerjee, C. Polychronopoulos","doi":"10.1145/1787275.1787302","DOIUrl":"https://doi.org/10.1145/1787275.1787302","url":null,"abstract":"Multi-cores such as the Intel Core 2 Duo, AMD Barcelona and IBM POWER6 are becoming ubiquitous. The number of cores and the resulting hardware parallelism is poised to increase rapidly in the foreseeable future. Nested thread-level speculative parallelization has been proposed as a means to exploit the hardware parallelism of such systems. In this paper, we present a methodology to gauge the efficacy of nested thread-level speculation with increasing level of nesting.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121714780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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