A. Brown, S. Furber, J. Reeve, P. Wilson, Mark Zwolinski, J. Chad, L. Plana, D. Lester
{"title":"A communication infrastructure for a million processor machine","authors":"A. Brown, S. Furber, J. Reeve, P. Wilson, Mark Zwolinski, J. Chad, L. Plana, D. Lester","doi":"10.1145/1787275.1787290","DOIUrl":null,"url":null,"abstract":"SpiNNaker (Spiking Neural Network architecture) is a massively parallel computing machine, comprising a million ARM9 cores. These are realised on 50000 chips, 20 cores/chip. While it could be classed as a MIMD machine, there is no unifying bus structure, and there is no attempt to maintain cross-system memory coherence. Inter-core communication is brokered by a fast message-passing system, built in and managed at the hardware level - thus there is an inevitable tension between speed and flexibility. The message passing infrastructure was designed to be fast and have a high bandwidth; a consequence of this design decision is that the effective data payload is only 32 bits/packet. Whilst this is ample for a wide range of applications, when the system is initialising, it is necessary to transport relatively large and sophisticated data structures across the system. This can be slow and cumbersome, and makes some form of internal self-organisation extremely attractive. This is described in outline here.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 7th ACM international conference on Computing frontiers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1787275.1787290","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
SpiNNaker (Spiking Neural Network architecture) is a massively parallel computing machine, comprising a million ARM9 cores. These are realised on 50000 chips, 20 cores/chip. While it could be classed as a MIMD machine, there is no unifying bus structure, and there is no attempt to maintain cross-system memory coherence. Inter-core communication is brokered by a fast message-passing system, built in and managed at the hardware level - thus there is an inevitable tension between speed and flexibility. The message passing infrastructure was designed to be fast and have a high bandwidth; a consequence of this design decision is that the effective data payload is only 32 bits/packet. Whilst this is ample for a wide range of applications, when the system is initialising, it is necessary to transport relatively large and sophisticated data structures across the system. This can be slow and cumbersome, and makes some form of internal self-organisation extremely attractive. This is described in outline here.