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2011 Brazilian Symposium on Computing System Engineering最新文献

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Contributions to Improvement of the Formal Properties Verification Process in AADL Programs 对改进AADL程序中正式属性验证过程的贡献
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.28
R. G. D. Oliveira, Gabriel Santos, J. Farines, L. Becker
{"title":"Contributions to Improvement of the Formal Properties Verification Process in AADL Programs","authors":"R. G. D. Oliveira, Gabriel Santos, J. Farines, L. Becker","doi":"10.1109/SBESC.2011.28","DOIUrl":"https://doi.org/10.1109/SBESC.2011.28","url":null,"abstract":"Assuring the correctness of a system's behavior is a must when dealing with critical systems. For instance, the Topcased project proposed several tools and methods in order to model such systems and to verify its behavior prior to implementation. In this scenario, the AADL modeling language plays a key role. Using this language, one can perform transformations to models with lower abstraction levels and perform the verification of properties. To ease this process, this paper presents a recently developed tool that provides a more intuitive way of constructing the sentences for property verification. It also helps the visualization of the verification results and enables to track the system's behavior from its initialization up to the point where the property couldn't be sustained. We illustrate its use and highlight its contributions with the modeling and verification of a pacemaker system.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132114888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
API for Performance Monitoring in Embedded Multicore Systems 嵌入式多核系统性能监控API
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.27
G. Gracioli, A. A. Fröhlich
{"title":"API for Performance Monitoring in Embedded Multicore Systems","authors":"G. Gracioli, A. A. Fröhlich","doi":"10.1109/SBESC.2011.27","DOIUrl":"https://doi.org/10.1109/SBESC.2011.27","url":null,"abstract":"Hardware Performance Counters (HPCs) are special registers available in the most modern processors that can be used to monitor shared hardware resources in multicore processors. Specifically for embedded real-time applications running on a multicore processor, such shared resources can affect their performance and cause deadline misses. This paper presents a hardware performance counter interface designed to embedded systems. The use of the interface is demonstrated through a benchmark that shares data between two threads executing in different cores of a multicore processor. As a result, the operating system can obtain an accurate view of software's behavior.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116219382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Opportunistic Networks: End-to-End Performance Analysis 机会主义网络:端到端性能分析
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.46
Rodrigo M. Santos, J. Orozco
{"title":"Opportunistic Networks: End-to-End Performance Analysis","authors":"Rodrigo M. Santos, J. Orozco","doi":"10.1109/SBESC.2011.46","DOIUrl":"https://doi.org/10.1109/SBESC.2011.46","url":null,"abstract":"In this paper, a real-time analysis of opportunistic networks is done. The worst case end-to-end delay is presented when there are special nodesnamed mules that are periodic and follow a fixed and known path. Necessaryand sufficient conditions for the schedulability of the system are presented sodeadlines can be guaranteed.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116545876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Formal Verification of UML Sequence Diagrams in the Embedded Systems Context 嵌入式系统环境中UML序列图的形式化验证
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.18
E. Cunha, Marcelo Custódio, Herbert Rocha, R. Barreto
{"title":"Formal Verification of UML Sequence Diagrams in the Embedded Systems Context","authors":"E. Cunha, Marcelo Custódio, Herbert Rocha, R. Barreto","doi":"10.1109/SBESC.2011.18","DOIUrl":"https://doi.org/10.1109/SBESC.2011.18","url":null,"abstract":"This paper shows a method for translating UML sequence diagrams to Petri nets and verifying deadlockfreeness, reachability, safety and liveness properties by using a model checker. In this proposed method, the user has not to know about temporal logics to describe the property to be verified. Instead, the user may adopt a high-level properties specification interface, which is automatically translated to a suitable temporal logic. We show the application of the proposed method in an embedded control application that consists of a sensory device mounted on a motorized platform that must detect and track specific objects in the environment.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129545896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Performance Analysis of the Sporadic Server Implementation in Real-Time Specification for Java Java实时规范中零星服务器实现的性能分析
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.15
Carlos M. Tripode, Rodrigo M. Santos, J. Orozco
{"title":"Performance Analysis of the Sporadic Server Implementation in Real-Time Specification for Java","authors":"Carlos M. Tripode, Rodrigo M. Santos, J. Orozco","doi":"10.1109/SBESC.2011.15","DOIUrl":"https://doi.org/10.1109/SBESC.2011.15","url":null,"abstract":"In this paper, we introduce the implementation ofthe Sporadic Server algorithm at the user level in Real TimeJava. That is, we do not modify the specification of the JavaVirtual Machine (JVM) so our proposal runs without problemson every JVM with support for real-time scheduling. The paperin- cludes an experimental evaluation of the aperiodic handlingmechanism using as benchmark the one developed for the RTSJ","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130642798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Minix over Linux: A User-Space Multiserver Operating System Minix over Linux:用户空间多服务器操作系统
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.17
P. Pessolani, Oscar Jara
{"title":"Minix over Linux: A User-Space Multiserver Operating System","authors":"P. Pessolani, Oscar Jara","doi":"10.1109/SBESC.2011.17","DOIUrl":"https://doi.org/10.1109/SBESC.2011.17","url":null,"abstract":"Minix is an open-source multiserver operating system designed to be highly reliable, flexible, and secure. The kernel is small and is the only piece of software that runs in privileged-mode, on the other hand user processes, specialized servers and device drivers run as isolated processes in user-mode. System Calls use Interprocess Communications primitives to send messages requesting services from the servers, and to wait for response messages. The aim of the project described in this article is a user-space multiserver operating system (a modified Minix version) running on top of a middleware-based virtual machine with simulated hardware constructed from services provided by a host operating system (Linux).","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129832318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
FARES: A Light Algorithm for Data Routing in Wireless Sensor Networks FARES:无线传感器网络中数据路由的轻量级算法
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.25
Felipe Bastos Nunes, Elias Teodoro da Silva Júnior, António Varela
{"title":"FARES: A Light Algorithm for Data Routing in Wireless Sensor Networks","authors":"Felipe Bastos Nunes, Elias Teodoro da Silva Júnior, António Varela","doi":"10.1109/SBESC.2011.25","DOIUrl":"https://doi.org/10.1109/SBESC.2011.25","url":null,"abstract":"This paper describes a development of a routing algorithm (FARES -- Alternated Flow in WSN) for Wireless Sensor Networks (WSN). The proposed algorithm avoids spreading replicated messages in the network, saving energy. Moreover, it deviates the message flow from dead or overwhelmed nodes, providing fault tolerance. At the end, the paper shows experimental results obtained by a network simulator.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133689666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Device Driver Generation and Checking Approach 设备驱动程序的生成和检查方法
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.24
R. Macieira, E. B. Lisboa, E. Barros
{"title":"Device Driver Generation and Checking Approach","authors":"R. Macieira, E. B. Lisboa, E. Barros","doi":"10.1109/SBESC.2011.24","DOIUrl":"https://doi.org/10.1109/SBESC.2011.24","url":null,"abstract":"Optimizing time and effort in embedded systems design is essential nowadays. The increased productivity gap together with the reduced time to market make the design of some components of the system the main design bottleneck.Taking into account the natural complexity of HdS design, a software checking technique helps finding bugs. However the increasing complexity of HdS makes the development and use of checking techniques a challenge.Reducing the time spent to build the checking environment can be a solution for this kind of problem. This can be accomplished by automating the generation of the checking environment from a device specification. The use of virtual platforms also represents an advantage since it supports to start the HdS development in an initial design phase.This paper proposes an approach for checking errors during the development of a very error prone Hardware dependent Software, that is device drivers. The proposed checking mechanism can be generated from a device specification using a language called Temporal DevC. Taking a device description in TDevC, the proposed approach generates a driver checking mechanism based on state machines. Experiments show the efficiency and effectiveness of the proposed mechanism, enabling its use for the detection of unwanted flows in the device driver simulation as well.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133799878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automatic Classification of Processes in a General-Purpose Operating System 通用操作系统中的进程自动分类
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.33
Priscila Vriesman Araujo, C. Maziero, J. C. Nievola
{"title":"Automatic Classification of Processes in a General-Purpose Operating System","authors":"Priscila Vriesman Araujo, C. Maziero, J. C. Nievola","doi":"10.1109/SBESC.2011.33","DOIUrl":"https://doi.org/10.1109/SBESC.2011.33","url":null,"abstract":"The scheduler's main goal in a general purpose multitasking operating system is to provide a fair share of processor time to all processes, in order to achieve good performance and an adequate response time for interactive applications. Each process has its own demands for processing and response time, which can not always easily be informed by the user or inferred by the scheduler itself. This article aims to explore the possibilities of applying data mining techniques to the mass of information held by the system kernel for each process, in order to 1) automatically discover groups of processes with similar behavior and 2) automatically classify new processes in these groups. The automatic classification of processes into groups of similar behavior can significantly assist the task of the process scheduler.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Case Study of AOP and OOP Applied to Digital Hardware Design 面向方面编程和面向对象编程在数字硬件设计中的应用
2011 Brazilian Symposium on Computing System Engineering Pub Date : 2011-11-07 DOI: 10.1109/SBESC.2011.23
T. Mück, M. Gernoth, Wolfgang Schröder-Preikschat, A. A. Fröhlich
{"title":"A Case Study of AOP and OOP Applied to Digital Hardware Design","authors":"T. Mück, M. Gernoth, Wolfgang Schröder-Preikschat, A. A. Fröhlich","doi":"10.1109/SBESC.2011.23","DOIUrl":"https://doi.org/10.1109/SBESC.2011.23","url":null,"abstract":"In this paper we explore a SystemC-based hardware design method which uses aspect-oriented programming concepts. We have designed a synthesizable resource scheduler at register transfer level by using only features available in the SystemC synthesizable subset. The results show that aspect-oriented programming applied to digital hardware design provides a better separation of concerns at the cost of a negligible overhead.","PeriodicalId":147899,"journal":{"name":"2011 Brazilian Symposium on Computing System Engineering","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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