Device Driver Generation and Checking Approach

Abstract

Optimizing time and effort in embedded systems design is essential nowadays. The increased productivity gap together with the reduced time to market make the design of some components of the system the main design bottleneck.Taking into account the natural complexity of HdS design, a software checking technique helps finding bugs. However the increasing complexity of HdS makes the development and use of checking techniques a challenge.Reducing the time spent to build the checking environment can be a solution for this kind of problem. This can be accomplished by automating the generation of the checking environment from a device specification. The use of virtual platforms also represents an advantage since it supports to start the HdS development in an initial design phase.This paper proposes an approach for checking errors during the development of a very error prone Hardware dependent Software, that is device drivers. The proposed checking mechanism can be generated from a device specification using a language called Temporal DevC. Taking a device description in TDevC, the proposed approach generates a driver checking mechanism based on state machines. Experiments show the efficiency and effectiveness of the proposed mechanism, enabling its use for the detection of unwanted flows in the device driver simulation as well.