Algorithmic Aspects of VLSI Layout最新文献

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Switch-Box Routing under the two-Overlap wiring Model 双重叠布线模式下的开关箱布线
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0009
T. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng
{"title":"Switch-Box Routing under the two-Overlap wiring Model","authors":"T. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng","doi":"10.1142/9789812794468_0009","DOIUrl":"https://doi.org/10.1142/9789812794468_0009","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131704415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Issues in Timing Driven Layout 时间驱动布局的问题
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0001
M. Marek-Sadowska
{"title":"Issues in Timing Driven Layout","authors":"M. Marek-Sadowska","doi":"10.1142/9789812794468_0001","DOIUrl":"https://doi.org/10.1142/9789812794468_0001","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114925999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Integer Program formulations of Global Routing and Placement Problems 全局路径与布局问题的整数规划公式
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0005
Thomas Lengauer, Martin Lügering
{"title":"Integer Program formulations of Global Routing and Placement Problems","authors":"Thomas Lengauer, Martin Lügering","doi":"10.1142/9789812794468_0005","DOIUrl":"https://doi.org/10.1142/9789812794468_0005","url":null,"abstract":"Received (received date) Revised (revised date) Communicated by (Name of Editor) ABSTRACT Global routing is an essential phase during the process of physical design of integrated circuits. Combinatorially, this problem amounts to a set of interdependent Steiner tree problems. Several versions of the problem are of importance in practical applications. All of them can be formulated as integer programs. Several such formulations have been investigated in the past, and diierent solution methods have been developed for diierent formulations. In this paper we give an overview of integer program formulations of the global routing problem and their solution methods, and we introduce new concepts for solving this important combinatorial problem. Finally, we present integer program formulations that integrate placement with global routing.","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131207767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Routing around two Rectangles to minimize the Layout Area 绕过两个矩形以最小化布局区域
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0014
T. Gonzalez, Sing-Ling Lee
{"title":"Routing around two Rectangles to minimize the Layout Area","authors":"T. Gonzalez, Sing-Ling Lee","doi":"10.1142/9789812794468_0014","DOIUrl":"https://doi.org/10.1142/9789812794468_0014","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131998249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan 一种用于VLSI平面设计的最大平面图中所有复杂三角形的消除算法
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0011
S. Tsukiyama, Keiichi Koike, I. Shirakawa
{"title":"An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan","authors":"S. Tsukiyama, Keiichi Koike, I. Shirakawa","doi":"10.1142/9789812794468_0011","DOIUrl":"https://doi.org/10.1142/9789812794468_0011","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114923329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A Survey of Parallel Algorithms for VLSI cell Placement VLSI单元放置并行算法综述
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0003
P. Banerjee
{"title":"A Survey of Parallel Algorithms for VLSI cell Placement","authors":"P. Banerjee","doi":"10.1142/9789812794468_0003","DOIUrl":"https://doi.org/10.1142/9789812794468_0003","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127204377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the Manhattan and knock-knee Routing Models 关于曼哈顿和膝盖的路由模型
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0008
D. Zhou, F. Preparata
{"title":"On the Manhattan and knock-knee Routing Models","authors":"D. Zhou, F. Preparata","doi":"10.1142/9789812794468_0008","DOIUrl":"https://doi.org/10.1142/9789812794468_0008","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114703993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Approximate solutions for Graph and Hypergraph Partitioning 图和超图划分的近似解
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0004
F. Makedon, S. Tragoudas
{"title":"Approximate solutions for Graph and Hypergraph Partitioning","authors":"F. Makedon, S. Tragoudas","doi":"10.1142/9789812794468_0004","DOIUrl":"https://doi.org/10.1142/9789812794468_0004","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Circuit Partitioning Algorithms based on Geometry Model 基于几何模型的电路划分算法
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0006
T. Asano, T. Tokuyama
{"title":"Circuit Partitioning Algorithms based on Geometry Model","authors":"T. Asano, T. Tokuyama","doi":"10.1142/9789812794468_0006","DOIUrl":"https://doi.org/10.1142/9789812794468_0006","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125274904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Binary formulations for Placement and Routing Problems 定位和路径问题的二元公式
Algorithmic Aspects of VLSI Layout Pub Date : 1900-01-01 DOI: 10.1142/9789812794468_0002
S. M. Kang, M. Sriram
{"title":"Binary formulations for Placement and Routing Problems","authors":"S. M. Kang, M. Sriram","doi":"10.1142/9789812794468_0002","DOIUrl":"https://doi.org/10.1142/9789812794468_0002","url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123542805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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