M. Marek-Sadowska
{"title":"Issues in Timing Driven Layout","authors":"M. Marek-Sadowska","doi":"10.1142/9789812794468_0001","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":145557,"journal":{"name":"Algorithmic Aspects of VLSI Layout","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Algorithmic Aspects of VLSI Layout","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1142/9789812794468_0001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12