2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)最新文献_第6页

ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems 混合临界实时系统中RED调度器的ASIC体系结构与实现

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2020-06-01 DOI: 10.23919/MIXDES49814.2020.9156070

L. Kohútka, V. Stopjaková

{"title":"ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems","authors":"L. Kohútka, V. Stopjaková","doi":"10.23919/MIXDES49814.2020.9156070","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9156070","url":null,"abstract":"This paper presents a new ASIC design of a coprocessor that performs process scheduling for embedded mixed-criticality real-time systems consisting of processes of various criticality and various real-time attributes. The proposed solution is implementing Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time processes. Thanks to the on-chip implementation of the scheduler in a form of a coprocessor, the scheduler operations can be completed in two clock cycles regardless of the process amount within the system contains. The proposed scheduler was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into an ASIC using 28 nm process by TSMC. Two versions of real-time process schedulers were compared: EDF scheduler designed for hard real-time processes only and the proposed RED scheduler. The RED algorithm handles variations of process execution times better, achieves higher CPU utilization and can be used for scheduling of hard real-time, soft real-time and non-real-time processes combined within one system that is not possible using the other scheduling algorithms.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126425868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A New Architecture of Thermometer to Binary Decoder in a Low-Power 6-bit 1.5GS/s Flash ADC 一种低功耗6位1.5GS/s Flash ADC中温度计到二进制解码器的新架构

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2020-06-01 DOI: 10.23919/MIXDES49814.2020.9155906

Mohammad Keyhanazar, A. Kalami, A. Amini

{"title":"A New Architecture of Thermometer to Binary Decoder in a Low-Power 6-bit 1.5GS/s Flash ADC","authors":"Mohammad Keyhanazar, A. Kalami, A. Amini","doi":"10.23919/MIXDES49814.2020.9155906","DOIUrl":"https://doi.org/10.23919/MIXDES49814.2020.9155906","url":null,"abstract":"This paper introduces a new structure of the thermometer to binary decoder utilizing combination of two conventional approach and modify them in a low-power 6-bit flash analog to digital converter (ADC). Considering advantages of each method to form the presented decoder can lead to minimum possible power consumption which is a critical parameter in all converters especially in flash ADCs. Moreover, in the high-resolution flash ADCs, the decoder structure will be simpler compared to conventional ones and decreases the amount of power dissipation as well. Simulation results through HSPICE software level 49 parameters in 0.18μm standard CMOS technology parameters, prove the precise operation and the great improvements. The 6-bit converter achieves sampling rate of 1.5 GS/s, and precision of 5.10 effective number of bits (ENOB). The proposed ADC works with 1.8V power supply and it has the power consumption of 4.57mW and the figure of merit (FOM) is 0.047 pJ/conversion-step. Hence, this architecture would be dedicated to communication transceivers and data acquisition systems where area and energy efficiency are paramount.","PeriodicalId":145224,"journal":{"name":"2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"9 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129072277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigations Properties of Selected Methods of Measurements of Thermal Parameters of the IGBT IGBT热参数测量方法的特性研究

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2020-06-01 DOI: 10.23919/MIXDES49814.2020.9155824

K. Górecki, P. Górecki

引用次数: 1

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2020-06-01 DOI: 10.23919/MIXDES49814.2020.9156069

M. Jezewski, R. Czabański, J. Leski, A. Matonia, R. Martínek

引用次数: 1

General Invited Papers 一般邀请文件

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/mixdes.2017.8004583

引用次数: 0

Microelectronics Technology and Packaging 微电子技术与封装

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2018-06-01 DOI: 10.1109/mixdes.2015.7208573

引用次数: 0

Thermal Issues in Microelectronics 微电子学中的热问题

2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/mixdes.2018.8436933

引用次数: 2