发布求助
文献互助 智能选刊 最新文献

2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

筛选
英文 中文
Electronic System Level Design of Heterogeneous Systems: a Motor Speed Control System Case Study 异构系统的电子系统级设计:一个电机速度控制系统案例研究
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961289
Breytner Fernández-Mesa, Liliana Andrade, F. Pétrot
{"title":"Electronic System Level Design of Heterogeneous Systems: a Motor Speed Control System Case Study","authors":"Breytner Fernández-Mesa, Liliana Andrade, F. Pétrot","doi":"10.1109/NEWCAS44328.2019.8961289","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961289","url":null,"abstract":"Although SystemC and its AMS extensions are widely promoted for the design of heterogeneous systems, very few complete cases studies are actually available. In this work, we present a digital and an analog version of a motor speed controller, and detail various modeling approaches. In the digital version, the executable specification is refined to a TLM virtual prototype that runs SW code on a QEMU emulated RISC-V, to study the effect of HW/SW design decisions on the physical system dynamics. In the analog version, the controller equation is mapped to a SystemC AMS model and refined from the discrete-time to the continuous-time domain. By simulating this system, we illustrate the effectiveness of SystemC and SystemC AMS for heterogeneous design space exploration. The example is available at https://gricad-gitlab.univ-grenoble-alpes.fr/tima/public/newcas2019","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116685781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 34-fJ/bit 20-Gb/s 1/8-rate Charge-Steering DFE for IoT Applications 用于物联网应用的34-fJ/bit 20gb /s 1/8速率电荷导向DFE
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961251
M. Saif, Khaled M. Hassan, Ahmed Abdelati, S. Ibrahim
{"title":"A 34-fJ/bit 20-Gb/s 1/8-rate Charge-Steering DFE for IoT Applications","authors":"M. Saif, Khaled M. Hassan, Ahmed Abdelati, S. Ibrahim","doi":"10.1109/NEWCAS44328.2019.8961251","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961251","url":null,"abstract":"The need for receiver equalization in wireline communication systems has increased with the large increase in data rates. There are two main categories for equalizers; continuous-time linear equalizers and non-linear equalizers implemented as decision feedback equalizers (DFE). Most DFEs use half-rate or quarter-rate architectures. The DFE proposed in this paper, however, uses a 1/8-rate architecture to relax the timing constraints and reduce power consumption. This paper presents the design of a 1-tap 20-Gb/s charge-steering 1/8-rate DFE in a 65-nm CMOS technology. The proposed DFE consumes 0.68-mW from a 1-V supply and compensates for 7-dB channel loss at Nyquist when processing 20-Gb/s data.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127529315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.5-V 180-nm CMOS Switched-Capacitor Temperature Sensor with 319 nJ/measurement 0.5 v 180纳米CMOS开关电容温度传感器，319 nJ/测量
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961301
Markus Stadelmayer, Thomas Faseth, H. Pretl
{"title":"A 0.5-V 180-nm CMOS Switched-Capacitor Temperature Sensor with 319 nJ/measurement","authors":"Markus Stadelmayer, Thomas Faseth, H. Pretl","doi":"10.1109/NEWCAS44328.2019.8961301","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961301","url":null,"abstract":"In this paper an ultra-low-power switched-capacitor (SC) temperature sensor realized in a 180 nm CMOS process is introduced. The sensor is operational at supply voltages down to 0.5 V, equivalent to the threshold voltages of the available MOS transistors. Using bipolar transistors for reference and temperature dependent voltage generation in a SC band-gap core, the overall temperature sensor is formed by a combination of the band-gap with a time-discrete pseudo-differential single-slope analog-to-digital converter. The temperature sensor has a power consumption of 2.62 µW (4.56 µW) including all biasing and clock generation at supply voltages of 0.5 V (0.8 V), and achieves an estimated 3σ accuracy of 2.42°C (1.36°C) using a two-point trim for the temperature range of 10°C to 100°C (−20°C to 100°C). Besides the temperature sensing functionality, the presented circuitry additionally provides a 24 kHz clock signal and stable reference voltage for other circuit blocks.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126766076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-Gating Models for Rapid Design Exploration 快速设计探索的功率门控模型
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961232
Dustin Peterson, O. Bringmann
{"title":"Power-Gating Models for Rapid Design Exploration","authors":"Dustin Peterson, O. Bringmann","doi":"10.1109/NEWCAS44328.2019.8961232","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961232","url":null,"abstract":"Power gating (PG) is an effective method to reduce leakage currents in an SoC design during run-time. It dynamically shuts down components using a network of sleep transistors but requires a detailed analysis to scale this network appropriately with respect to area wake-up time in-rush currents voltage drops and transition energies. In this paper we present a method to efficiently determine these key parameters for any SoC design and sleep transistor network at gate-level to enable the rapid exploration of power design alternatives while providing sufficient accuracy for high-level design exploration. Compared to SPICE our approach achieves a speed-up of up to 11457x for two ISCAS circuits a 32-bit multiplier and a RISC-V core each build for a 90nm PDK. The average error compared to SPICE is 2.6% for peak current and 10% for wake-up energy and delay.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115035530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Ultra-Broad-Band Low-Distortion High-Efficiency Class-D Power Amplifier in 130nm CMOS Technology 基于130nm CMOS技术的超宽带低失真高效d类功率放大器
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961223
A. Mamdouh, M. Aboudina, F. Hussien, A. Mohieldin
{"title":"An Ultra-Broad-Band Low-Distortion High-Efficiency Class-D Power Amplifier in 130nm CMOS Technology","authors":"A. Mamdouh, M. Aboudina, F. Hussien, A. Mohieldin","doi":"10.1109/NEWCAS44328.2019.8961223","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961223","url":null,"abstract":"This paper presents a novel design of an ultra-broad-band class-D power amplifier (PA). The proposed architecture is based on the concept of the ripple buck converter after employing some modifications to facilitate supporting bandwidths up to tens of MHz. The input frequency range covered using the proposed class-D PA is from 0.5MHz up to 30MHz. A wide-band transformer has been used to convert the differential outputs of the class-D PA to single-ended load. The design has been implemented and fabricated using a CMOS 0.13µm technology. It occupies an active area of 0.836mm2 and operates from a single 1.2V supply. The measurement results validates the functionality of the proposed class-D PA with good linearity and peak efficiency of 58% at 140mW of output power. This has been achieved using few off-chip passive components.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122358268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Local Organizer 当地组织者
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/newcas44328.2019.8961215
Antonio Celani Ictp
{"title":"Local Organizer","authors":"Antonio Celani Ictp","doi":"10.1109/newcas44328.2019.8961215","DOIUrl":"https://doi.org/10.1109/newcas44328.2019.8961215","url":null,"abstract":"Lucy Aplin (University of Oxford) Nicolas Bredeche (UPMC) Andrea Cavagna (CNR, Rome) Hugues Chaté (CEA) Gonzalo De Polavieja (Champalimaud Foundation) Audrey Dussutour (Université Toulouse III) Ofer Feinerman (Weizmann Institute of Science) Francesco Ginelli (University of Aberdeen) Deborah M. Gordon (Stanford University) Roderich Gross (University of Sheffield) Takashi Ikegami (University of Tokyo) Naomi E. Leonard (Princeton University) M. Cristina Marchetti (Syracuse University) Patrizio Mariani (Technical University of Denmark) James Marshall (University of Sheffield) Thierry Mora (ENS) Melanie E. Moses (University of New Mexico) Thomas Schmickl (University of Graz) Ariana Strandburg-Peshkin (Max Planck Institute for Ornithology) Guy Theraulaz (Université Toulouse III) Shashi Thutupalli (SCSLM, NCBS, ICTS) Colin Torney (University of Glasgow) Tamás Vicsek (Eötvös University Budapest) Aleksandra Walczak (ENS) Justin Werfel (Harvard University) 7 11 May 2018 Trieste, Italy","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114429172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards accurate camera-less eye tracker using instrumented contact lens 向使用仪器隐形眼镜的精确无摄像头眼动仪迈进
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961304
L. Massin, C. Lahuec, Vincent Nourrit, F. Seguin, Jean-Louis de Bougrenet
{"title":"Towards accurate camera-less eye tracker using instrumented contact lens","authors":"L. Massin, C. Lahuec, Vincent Nourrit, F. Seguin, Jean-Louis de Bougrenet","doi":"10.1109/NEWCAS44328.2019.8961304","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961304","url":null,"abstract":"This paper presents a camera-less eye tracker. Composed of 2 parts, an instrumented contact lens and spectacles, its principle consists in computing a barycenter based on the light intensity variations received from the spectacles onto the lens. To demonstrate both the method and the achieved accuracy it yields, a prototype lens fitted with 4 infrared sensors has been fabricated and tested. Based on measured photo-currents, simulations, both behavioral and at transistor level (AMS 0.35 µm CMOS), show an accuracy of 0.1° can be achieved. Which is a significant improvement to the 1° camera-base eye trackers offer.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Physically-Derived 3-Box Power Amplifier Model 物理推导的3箱功率放大器模型
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961231
E. Soleiman, Dang-Kièn Germain Pham, C. Jabbour, P. Desgreys, M. Kamarei
{"title":"Physically-Derived 3-Box Power Amplifier Model","authors":"E. Soleiman, Dang-Kièn Germain Pham, C. Jabbour, P. Desgreys, M. Kamarei","doi":"10.1109/NEWCAS44328.2019.8961231","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961231","url":null,"abstract":"In this work, a novel approach to reduce the complexity of memory polynomial model is presented. The proposed technique, named the coefficient decomposition (CD) technique, is based on reducing the search space for the memory polynomial coefficients based on memory effects generation mechanism. In this paper, the technique is demonstrated for power amplifier of classes A and AB. In this case, the physical analysis shows that the conventional two-dimensional coefficient architecture of the memory polynomial could be simplified into a one dimensional architecture while keeping almost the same accuracy. The performance of the proposed approach is demonstrated and compared with other models using a 30 dBm commercial power amplifier with 20 MHz and 60 MHz LTE signals. The measurements and simulations showed that, the presented model achieves −34.2 dB of NMSE while needing only 13 coefficients compared with 25 needed for a memory polynomial model. Also, the DPD performance of the proposed model is the same as memory polynomial model and comparable with high complexity models like the PLUME and GMP.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129599636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping 全数字锁相环阵列:通过FPGA原型研究同步和抖动性能
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961269
Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina
{"title":"All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping","authors":"Eugene Koskin, P. Bisiaux, D. Galayko, E. Blokhina","doi":"10.1109/NEWCAS44328.2019.8961269","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961269","url":null,"abstract":"In this paper, we study the propagation of timing error in a synchronous All-Digital Phase-Locked Loop network. The architecture of the network represents a linear array of oscillators, where the first oscillator is considered as the reference oscillator, and the others are implemented as digitally controlled oscillators. The synchronisation of the network is achieved through interactions between a controlled oscillator and its closest neighbours. Using FPGA prototyping, we have shown that the jitter of a controlled oscillator saturates with the distance from the reference oscillators and that the bidirectional topology has better performance than the unidirectional topology. A comparison of measurements with a theoretical model is carried out to verify our FPGA prototyping framework.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Self-Calibrating Digital-to-Time Converter in CMOS for Advanced Control in Smart Gate Drivers 用于智能栅极驱动器高级控制的CMOS自校准数时转换器
2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2019-06-01 DOI: 10.1109/NEWCAS44328.2019.8961303
Eva Schulte Bocholt, Leo Rolff, R. Wunderlich, S. Heinen
{"title":"Self-Calibrating Digital-to-Time Converter in CMOS for Advanced Control in Smart Gate Drivers","authors":"Eva Schulte Bocholt, Leo Rolff, R. Wunderlich, S. Heinen","doi":"10.1109/NEWCAS44328.2019.8961303","DOIUrl":"https://doi.org/10.1109/NEWCAS44328.2019.8961303","url":null,"abstract":"Time resolution is a major issue for smart gate drivers. These offer the potential to significantly increase switching performance of power switches. The proposed self-calibrating digital-to-time converter achieves a time resolution of less than 250ps, consuming less than 0.2mW of power when constantly activated. Thereby, the necessary timing resolution and range is achieved, that enables soft switching of power MOSFETs and SiC devices and can further increases the switching performance of IGBT.","PeriodicalId":144691,"journal":{"name":"2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124604506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信