2016 IEEE Applied Power Electronics Conference and Exposition (APEC)最新文献_第2页

Analytical model of a phase-shift controlled three-level zero-voltage switching converter 相移控制三电平零电压开关变换器的解析模型

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468210

C. Bakker, B. Vermulst, A. Driessen

引用次数: 2

Digitized self-oscillating loop for piezoelectric transformer-based power converters 基于压电变压器的电力变换器的数字化自振荡回路

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468056

Marzieh Ekhtiari, T. Andersen, Zhe Zhang, M. Andersen

引用次数: 3

Integrated DC-DC converter design for Electric Vehicle powertrains 电动汽车动力系统集成DC-DC变换器设计

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467907

Saeed Anwar, Weimin Zhang, Fred Wang, D. Costinett

引用次数: 18

Temperature-dependent turn-on loss analysis for GaN HFETs GaN hfet的温度依赖性导通损耗分析

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467994

E. Jones, Fred Wang, D. Costinett, Zheyu Zhang, Ben Guo

引用次数: 36

EMC investigation of a Very High Frequency self-oscillating resonant power converter 甚高频自振荡谐振功率变换器的电磁兼容性研究

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468072

Jeppe Pedersen, A. Knott, M. Andersen

引用次数: 0

Analysis of thermal cycling stress on semiconductor devices of the Modular Multilevel Converter for drive applications 驱动用模块化多电平变换器半导体器件的热循环应力分析

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468283

Xiangyu Han, Qichen Yang, L. Wu, M. Saeedifard

引用次数: 9

Comprehensive parametric analyses of thermally aged power MOSFETs for failure precursor identification and lifetime estimation based on gate threshold voltage 基于门阈值电压的热老化功率mosfet失效前兆识别和寿命估计的综合参数分析

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468158

S. Dusmez, B. Akin

{"title":"Comprehensive parametric analyses of thermally aged power MOSFETs for failure precursor identification and lifetime estimation based on gate threshold voltage","authors":"S. Dusmez, B. Akin","doi":"10.1109/APEC.2016.7468158","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468158","url":null,"abstract":"Thermal/power cycles are widely acknowledged methods to accelerate the package related extrinsic failures. Many studies have focused on particular failure precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements such as on-state resistance. In this paper, a custom-designed test bed is used to age a number of power MOSFETs and an automated curve tracer is utilized to capture parametric variations in I-V curves, transfer capacitances and gate charges at certain time intervals throughout the aging. The results suggest that the failure precursors which exhibit continuously increasing trend are the on-state resistance, body diode voltage drop, parasitic capacitances and threshold voltage. Based on the results, an exponential empirical model for the gate threshold voltage that fits successfully with the experimental data is proposed. Furthermore, Kalman Filter is employed to filter out the measurement noise and model uncertainties, which is also used to estimate the remaining useful lifetime of the degraded switches.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123279617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Clarification of relationship between current ripple and power density in bidirectional DC-DC converter 澄清双向DC-DC变换器中电流纹波与功率密度的关系

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468130

H. Le, K. Orikawa, J. Itoh

{"title":"Clarification of relationship between current ripple and power density in bidirectional DC-DC converter","authors":"H. Le, K. Orikawa, J. Itoh","doi":"10.1109/APEC.2016.7468130","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468130","url":null,"abstract":"This paper clarifies the relationship between the current ripple and the power density in bidirectional DC-DC converters. In the conventional power density design method, in order to obtain the pareto-front curve of the power density and the efficiency, the current ripple is designed as constant value, whereas the switching frequency is varied. As a result, the possibilities of higher power density or higher efficiency at different current ripple are not considered. Therefore, in this paper, the current ripple is also varied in order to evaluate all the designable power density. Specifically, a design flow chart is introduced to show step-by-step how to express all the losses and the volume of the converter as functions of the current ripple. Several 1-kW prototypes are constructed in order to confirm the validity of the design flow chart. By varying the current ripple, the highest power density of 10.1 kW/dm3 with the efficiency of 98.55% is achieved at the current ripple of 60%. Furthermore, the maximum error between the calculated and experimental power density and efficiency are 19.5% and 0.22 pt. respectively.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Synchronization strategies in cascaded H-Bridge multi level inverters for carrier based sinusoidal PWM techniques 基于载波正弦脉宽调制技术的级联h桥多电平逆变器同步策略

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467873

S. Sahoo, T. Bhattacharya

引用次数: 10

Phase compensation, ZVS operation of wireless power transfer system based on SOGI-PLL 基于SOGI-PLL的无线电力传输系统的相位补偿、ZVS操作

2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468320

Ping-an Tan, Haibing He, Xieping Gao

{"title":"Phase compensation, ZVS operation of wireless power transfer system based on SOGI-PLL","authors":"Ping-an Tan, Haibing He, Xieping Gao","doi":"10.1109/APEC.2016.7468320","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468320","url":null,"abstract":"Wireless power transfer (WPT) technology is now recognized as an efficient means of transferring power because having numerous advantages over conventional wired power transfer system. The phase delays, for example induced in the sampling process, the algorithm implementation process, the signal transduction process, etc. are widely found during the implementation of WPT system, which significantly degrade the system performance. Moreover, it would be extremely necessary to implement the Soft-Switching of the converter and the necessary dead time imposed by the drivers should be compatible with the resonant current phase lag control. This paper proposes a Direct Phase Control (DPC) approach, based on Second-Order Generalized Integrator Phase-Locked Loop (SOGI-PLL), to provide accurate phase compensation and stable ZVS operation in the WPT. The DPC determines the phase difference Δθ of WPT, which include the phase difference θι between the output voltage and current of the converter and the phase delay θ\"ι derived from the sampling process. The SOGI-PLL provides the phase of system for adjusting the output voltage frequency of the converter dynamically. Experimental results convincingly demonstrate that with the proposed method the phase delay can be compensated accurately and the ZVS operation can be achieved simultaneously.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116004836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13