{"title":"An O(log N log log N) time RMESH algorithm for the simple polygon visibility problem","authors":"Sung-Ryul Kim, Kunsoo Park, Yookun Cho","doi":"10.1109/ISPAN.1994.367152","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367152","url":null,"abstract":"In this paper we consider the simple polygon visibility problem: Given a simple polygon P with N vertices and a point z in the interior of the polygon, find all the boundary points of P that are visible from z. We present an O(logN loglogN) time algorithm that solves the simple polygon visibility problem on a /spl radic/N/spl times//spl radic/N RMESH. Previously, the best known algorithm for the problem on a /spl radic/N/spl times//spl radic/N RMESH takes O(log/sup 2/ N) time.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116689980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel hypercube with lower latency","authors":"A. Ahmed","doi":"10.1109/ISPAN.1994.367172","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367172","url":null,"abstract":"In this paper, we present a hypercube with reduced diameter and latencies. This is achieved by reconnecting the hypercube with twisted and random connections while keeping the number of wires constant. This new topology is called RT-cube. The RT-cubes offer smaller diameter and reduced latencies compared to the normal hypercubes, resulting in a faster interconnection network topology. A packet switched routing algorithm and the router design model is also proposed for message passing in RT-cubes. The simulations and analysis have shown that RT-cube based proposed communication architecture is faster than the conventional hypercubes with the same wire cost, and scales well for massively parallel computing systems.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116112018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A performance evaluation procedure for a class of growable ATM switches","authors":"Z. Tsai, K. Yu, F. Lai","doi":"10.1109/ISPAN.1994.367186","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367186","url":null,"abstract":"We propose a modular ATM switching network by modifying the original delta network. It is composed of several stages of switching modules, and all the switching modules are of the same type of basic building block. In order to improve the performance, the channel group connecting the switching modules in all stages are expanded to contain more then one link. The switching system is in fact a discrete-time queueing network, and each output of a particular switching module is modeled as a finite buffer, multi-server queue with multiple cell arrival streams. We obtain a general performance evaluation procedure for such a multi-stage, self-routing switching system.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122298183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A greedy task clustering heuristic that is provably good","authors":"M. Palis, Jing-Chiou Liou, David S. L. Wei","doi":"10.1109/ISPAN.1994.367174","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367174","url":null,"abstract":"A simple greedy algorithm is presented for task clustering with duplication (or recomputation) which, for a task graph with arbitrary granularity, produces a schedule whose makespan is at most twice optimal. Furthermore, the quality of the schedule improves as the granularity of the task graph increases. For example, if the granularity is at least 1/2 , the makespan of the schedule is at most 5/3 times optimal. For a task graph with n tasks and e inter-task communication constraints, the algorithm runs in O(n(n lg n+e)) time, which is n times faster than the currently best known algorithm for this problem. Similar algorithms are developed that produce: (1) optimal schedules for coarse grain graphs; (2) 2-optimal schedules for trees with no task duplication; and (3) optimal schedules for coarse grain trees with no task duplication.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi-Wen Chen, S. Horng, T. Kao, Horng-Ren Tsai, S. Tsai
{"title":"Parallel connectivity algorithms on permutation graphs","authors":"Yi-Wen Chen, S. Horng, T. Kao, Horng-Ren Tsai, S. Tsai","doi":"10.1109/ISPAN.1994.367159","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367159","url":null,"abstract":"In this paper, we shall present several algorithms for determining the maximum number of vertex connectivity, testing k-vertex connectivity, determining the maximum number of vertex disjoint s-t paths and finding k-vertex disjoint s-t paths problems on a permutation graph, respectively. We first give several O(n/sup 2/) time sequential algorithms for determining the maximum number of vertez connectivity, testing k-vertex connectivity and determining the maximum number of vertex disjoint s-t paths problems, respectively. Then, an O(kn/sup 2/) time algorithm for finding k-vertex disjoint s-t paths problem on a permutation graph is also proposed. Moreover, we also derive the corresponding parallel algorithms for these problems from the proposed sequential algorithms. On the EREW PRAM model, we first propose several O(log n) time optimal speed-tip parallel algorithms for determining the maximum m number of vertez connectivity, testing k-vertex connectivity and determining the maximum number of vertex disjoint s-t paths problems, all with O(n/sup 2/log n) processors, respectively. Then, an O(nlog n) time parallel algorithm for finding k-vertex disjoint s-t paths problem using O(n/sup 2/log n) processors is also developed, where k is a fixed integer.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compiler-chosen operator granularity in a functionally-programmed tagged token architecture","authors":"G. Jennings","doi":"10.1109/ISPAN.1994.367182","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367182","url":null,"abstract":"In a recently proposed parallel execution model, operators as well as data operands are dynamically generated at execution time, and enter a special matching store which must accommodate either operator or operands arriving first in time. Here, we extend this execution model to permit the compiler to adjust the granularity of scheduled units emerging from the matching store, a problem which is complicated by the increased dynamics of the proposed execution model. Compiler output code is described in detail. Effects of different fragmentations on program speed and resource requirements are examined, using architectural simulations for a number of application programs compiled using different fragmentation methods. Architectural implications are discussed.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128355459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Adaptive fault-tolerant wormhole routing algorithms with low virtual channel requirements","authors":"S. Chalasani, R. Boppana","doi":"10.1109/ISPAN.1994.367144","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367144","url":null,"abstract":"We present simple methods to enhance a recently proposed class of fully adaptive algorithms for fault tolerant wormhole routing. These algorithms are based on J. Duato's (1993) theory and are being used in several research projects. We show that with three virtual channels per physical channel, multiple rectangular shaped fault blocks can be tolerated in two dimensional meshes. There is no restriction on the number of faults, and maintaining fault information locally is sufficient. The logic for fault tolerant routing is used only in the presence of faults, and there is no performance degradation in the absence of faults. The proposed technique incorporates fault tolerance into wormhole algorithms with simple logic and low virtual channel requirements.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115078475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An algorithm for maintaining consistent view of processes in distributed systems","authors":"D. Hung","doi":"10.1109/ISPAN.1994.367167","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367167","url":null,"abstract":"In the paper, the problem of determining the global properties of distributed systems is addressed. At each moment during the execution of a system, every process has its knowledge about the system. By message passing the processes can exchange their knowledge. We present a general algorithm for a process to synthesize the knowledge that it obtains, and to maintain its consistent view about the system. Depending on different interpretations the algorithm can be used for distributed snapshots, for verification and design of stabilizing protocols, etc.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123712226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bounds on the VLSI layout complexity of homogeneous product networks","authors":"Antonio Fernández, K. Efe","doi":"10.1109/ISPAN.1994.367166","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367166","url":null,"abstract":"In this paper we obtain bounds on the area and wire length required by VLSI layouts of homogeneous product networks with any number of dimensions. The lower bounds are obtained by computing lower bounds on the bisection width and the crossing number. The upper bounds are derived by using traditional frameworks like separators and bifurcators, as well as a new method based on combining collinear layouts. This last method has led to the best area and wire lengths for most of the homogeneous product networks we considered.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal parallel algorithm for edge-coloring partial k-trees with bounded degrees","authors":"Xiaoping Zhou, Takao Nishizeki","doi":"10.1109/ISPAN.1994.367150","DOIUrl":"https://doi.org/10.1109/ISPAN.1994.367150","url":null,"abstract":"Many combinatorial problems can be efficiently solved for partial k-trees (graphs of treewidth bounded by k). The edge-coloring problem is one of the well-known combinatorial problems for which no NC algorithms have been obtained for partial k-trees. This paper gives an optimal and first NC parallel algorithm to find an edge-coloring of any given partial k-tree using a minimum number of colors if k and the maximum degree /spl Delta/ are bounded.<<ETX>>","PeriodicalId":142405,"journal":{"name":"Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121167307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}