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Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94最新文献

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A mismatch independent DNL-pipelined analog to digital converter 一个不匹配独立的dnl流水线模拟数字转换器
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409410
John Wu, B. Leung, S. Sutarja
{"title":"A mismatch independent DNL-pipelined analog to digital converter","authors":"John Wu, B. Leung, S. Sutarja","doi":"10.1109/ISCAS.1994.409410","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409410","url":null,"abstract":"A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes, the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be-realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 /spl mu/m CMOS process show that 3.3 MSamples/s can be resolved at 20 mW per bit.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Improved two-layer coding schemes for motion picture sequences 改进的电影序列双层编码方案
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409138
Shang-Pin Chang, Tsorng-Yang Mei, H. Hang
{"title":"Improved two-layer coding schemes for motion picture sequences","authors":"Shang-Pin Chang, Tsorng-Yang Mei, H. Hang","doi":"10.1109/ISCAS.1994.409138","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409138","url":null,"abstract":"This paper proposes several improved schemes on the two-layer codec. In a two-layer coder, the packets produced by the base layer are set to the high priority and those produced by the second layer are low. Three improved schemes on the base layer are proposed. The base layer bits and/or the total bits have been significant reduced by these improved algorithms. In addition, the base images have been also remarkably enhanced.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114585318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A simultaneous placement and global routing algorithm for FPGAs fpga的同步布局和全局路由算法
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.408843
N. Togawa, M. Sato, T. Ohtsuki
{"title":"A simultaneous placement and global routing algorithm for FPGAs","authors":"N. Togawa, M. Sato, T. Ohtsuki","doi":"10.1109/ISCAS.1994.408843","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.408843","url":null,"abstract":"An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Multiport memory based data path allocation focusing on interconnection optimization 基于多端口内存的数据路径分配，重点关注互连优化
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.408751
J. Jou, Ren-Der Chen, Shiann-Rong Kuang
{"title":"Multiport memory based data path allocation focusing on interconnection optimization","authors":"J. Jou, Ren-Der Chen, Shiann-Rong Kuang","doi":"10.1109/ISCAS.1994.408751","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.408751","url":null,"abstract":"A method based on the 0-1 integer linear programming (ILP) model aiming primarily at minimizing the cost of interconnections is proposed for solving the data path allocation problem using multiport memories. The interconnection elements are generally composed of buses, multiplexers, and tri-state buffers. After solving the operation binding problem, we first find the number of buses required. Then we deal with the multiport memory allocation problem simultaneously minimizing the cost of multiplexers and tri-state buffers. From the solution quality and execution time of the experimental results, we see that our method is suitable for solving data path allocation problem using multiport memories when the cost of interconnections is first considered.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fast radix 4 division algorithm 一个快速的基数4除法算法
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409259
H. Srinivas, K. Parhi
{"title":"A fast radix 4 division algorithm","authors":"H. Srinivas, K. Parhi","doi":"10.1109/ISCAS.1994.409259","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409259","url":null,"abstract":"In this paper we present a fast radix 4 division algorithm for floating point numbers based on Svoboda's division algorithm. The algorithm involves a simple recurrence with carry-free addition and employs pre-scaling of the operands, The quotient digits are determined by observing three most-significant radix 2 digits (msds) of the partial remainder and independent of the divisor. The proposed algorithm is faster than previously proposed radix 4 and radix 2 division algorithms, which require at least four digits of the partial remainder to be observed to determine a quotient digit. The speedup is achieved at cost of increase in area.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130828048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A standardized interface control unit for heterogeneous digital signal processors 异构数字信号处理器的标准化接口控制单元
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.408914
Mohammad S. Khan, E. Swartzlander
{"title":"A standardized interface control unit for heterogeneous digital signal processors","authors":"Mohammad S. Khan, E. Swartzlander","doi":"10.1109/ISCAS.1994.408914","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.408914","url":null,"abstract":"An approach is presented for the implementation of high-performance heterogeneous digital signal processors. This approach facilitates tailoring the configuration of the hardware to the signal flow graph of the application. The hardware system comprises heterogeneous processors which are specialized for performing a predefined set of functions. The focus of this research is to solve the communication problems associated with the interconnection of the heterogeneous building blocks to implement application-specific systems. An interface control unit (ICU) architecture is proposed that allows the interconnection of processors with varying speeds and functionalities. A protocol has been developed that facilitates transfer of large data blocks in sparse networks. The hardware design and implementation of the ICU is based on this protocol. The digital design of the ICU is suitable for fabrication as a single VLSI circuit.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124573287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing 用叠块处理计算二维离散小波变换中最小寄存器数
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409107
T. C. Denk, K. Parhi
{"title":"Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing","authors":"T. C. Denk, K. Parhi","doi":"10.1109/ISCAS.1994.409107","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409107","url":null,"abstract":"This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130839678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
VHF/UHF high-Q bandpass tunable filters design using CMOS-inverter-based transresistance amplifiers VHF/UHF高q带通可调谐滤波器设计采用基于cmos逆变器的跨电阻放大器
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409456
P. Lu, Chung-Yu Wu, M. Tsai
{"title":"VHF/UHF high-Q bandpass tunable filters design using CMOS-inverter-based transresistance amplifiers","authors":"P. Lu, Chung-Yu Wu, M. Tsai","doi":"10.1109/ISCAS.1994.409456","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409456","url":null,"abstract":"A new CMOS inverter-based wideband transresistance (R/sub m/) amplifier is proposed and analyzed. Using the R/sub m/ amplifier, tunable VHF/UHF R/sub m/-C bandpass biquadratic filters can be designed. In these filters, the center frequency f/sub 0/ can be post-tuned by adjusting the control voltages of the R/sub m/ amplifier. Experimental results have shown that the single-ended-output R/sub m/-C bandpass biquad has the center frequency f/sub 0/=368 MHz and the quality factor Q=1.95 whereas the fully-differential-output configuration has Q=360 and f/sub 0/=222.7 MHz.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130566978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Array based fuzzy inference mechanism implemented with current mode CMOS circuits 基于阵列的模糊推理机制采用电流型CMOS电路实现
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409431
Bin-Da Liu, Chun-Yueh Huang
{"title":"Array based fuzzy inference mechanism implemented with current mode CMOS circuits","authors":"Bin-Da Liu, Chun-Yueh Huang","doi":"10.1109/ISCAS.1994.409431","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409431","url":null,"abstract":"This paper presents an array based structure for the fuzzy inference mechanism which is implemented by current-mode circuits. Since the computations of the fuzzy relation and fuzzy inference are in parallel, the inference speed is high and the inference structure is suitable for real-time processing.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132881788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The continuous-time VHF lowpass filter design using finite-gain current and voltage amplifiers and special Q-enhancement circuit 采用有限增益电流和电压放大器和专用增q电路设计了VHF连续时间低通滤波器
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 Pub Date : 1994-12-01 DOI: 10.1109/ISCAS.1994.409492
Chung-Yu Wu, Heng-Shou Hsu
{"title":"The continuous-time VHF lowpass filter design using finite-gain current and voltage amplifiers and special Q-enhancement circuit","authors":"Chung-Yu Wu, Heng-Shou Hsu","doi":"10.1109/ISCAS.1994.409492","DOIUrl":"https://doi.org/10.1109/ISCAS.1994.409492","url":null,"abstract":"A linear wideband class AB finite-gain current amplifier is proposed and analyzed. Considering the intrinsic capacitance of the MOS transistors as filter elements, the current amplifier can be viewed as a VHF lowpass biquad filter. The center frequency fo is tunable from 79.4 MHz to 144.5 MHz and the quality factor Q is tunable from 1.03 to 1.19. A linear wideband class AB finite-gain voltage amplifier is also proposed and analyzed. Similarly, the unity-gain voltage amplifier can also be regarded as a VHF voltage biquad lowpass filter with the center frequency tunable from 81 MHz to 134.89 MHz and the quality factor tunable from 1.12 to 1.59. A new and special Q-enhancement circuit is also proposed to increase the center frequency fo and enhance the quality factor Q of the VHF filters. It is shown that the center frequency fo is tunable from 173.78 MHz to 205.6 MHz and the quality factor Q tunable from 1.69 to 7.21.<<ETX>>","PeriodicalId":140999,"journal":{"name":"Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123411360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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