ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195538

K. Hayashi, Tsunehisa Doi, T. Horie, Y. Koyanagi, Osamu Shiraki, Nobutaka Imamura, T. Shimizu, H. Ishihata, Tatsuya Shindo

引用次数: 34

Hardware and software support for efficient exception handling 硬件和软件支持有效的异常处理

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195515

C. Thekkath, H. Levy

引用次数: 93

Software overhead in messaging layers: where does the time go? 消息传递层中的软件开销:时间都去哪儿了?

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195499

V. Karamcheti, A. Chien

引用次数: 110

Hardware support for fast capability-based addressing 硬件支持基于功能的快速寻址

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195579

N. Carter, S. Keckler, W. Dally

{"title":"Hardware support for fast capability-based addressing","authors":"N. Carter, S. Keckler, W. Dally","doi":"10.1145/195473.195579","DOIUrl":"https://doi.org/10.1145/195473.195579","url":null,"abstract":"Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to record access permissions for processes. With the advent of computers that supported cycle-by-cycle multithreading, protection schemes that increase the time to perform a context switch are unacceptable, but protecting unrelated processes from each other is still necessary if such machines are to be used in non-trusting environments.\u0000This paper examines guarded pointers, a hardware technique which uses tagged 64-bit pointer objects to implement capability-based addressing. Guarded pointers encode a segment descriptor into the upper bits of every pointer, eliminating the indirection and related performance penalties associated with traditional implementations of capabilities. All processes share a single 54-bit virtual address space, and access is limited to the data that can be referenced through the pointers that a process has been issued. Only one level of address translation is required to perform a memory reference. Sharing data between processes is efficient, and protection states are defined to allow fast protected subsystem calls and create unforgeable data keys.","PeriodicalId":140481,"journal":{"name":"ASPLOS VI","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129383801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 135

The effectiveness of multiple hardware contexts 多硬件上下文的有效性

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195583

R. Thekkath, S. Eggers

{"title":"The effectiveness of multiple hardware contexts","authors":"R. Thekkath, S. Eggers","doi":"10.1145/195473.195583","DOIUrl":"https://doi.org/10.1145/195473.195583","url":null,"abstract":"Multithreaded processors are used to tolerate long memory latencies. By executing threads loaded in multiple hardware contexts, an otherwise idle processor can keep busy, thus increasing its utilization. However, the larger size of a multi-thread working set can have a negative effect on cache conflict misses. In this paper we evaluate the two phenomena together, examining their combined effect on execution time.\u0000The usefulness of multiple hardware contexts depends on: program data locality, cache organization and degree of multiprocessing. Multiple hardware contexts are most effective on programs that have been optimized for data locality. For these programs, execution time dropped with increasing contexts, over widely varying architectures. With unoptimized applications, multiple contexts had limited value. The best performance was seen with only two contexts, and only on uniprocessors and small multiprocessors. The behavior of the unoptimized applications changed more noticeably with variations in cache associativity and cache hierarchy, unlike the optimized programs.\u0000As a mechanism for exploiting program parallelism, an additional processor is clearly better than another context. However, there were many configurations for which the addition of a few hardware contexts brought as much or greater performance than a larger multiprocessor with fewer than the optimal number of contexts.","PeriodicalId":140481,"journal":{"name":"ASPLOS VI","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115111252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 82

Scheduling and page migration for multiprocessor compute servers 多处理器计算服务器的调度和页面迁移

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195485

Rohit Chandra, Scott Devine, Ben Verghese, Anoop Gupta, M. Rosenblum

{"title":"Scheduling and page migration for multiprocessor compute servers","authors":"Rohit Chandra, Scott Devine, Ben Verghese, Anoop Gupta, M. Rosenblum","doi":"10.1145/195473.195485","DOIUrl":"https://doi.org/10.1145/195473.195485","url":null,"abstract":"Several cache-coherent shared-memory multiprocessors have been developed that are scalable and offer a very tight coupling between the processing resources. They are therefore quite attractive for use as compute servers for multiprogramming and parallel application workloads. Process scheduling and memory management, however, remain challenging due to the distributed main memory found on such machines. This paper examines the effects of OS scheduling and page migration policies on the performance of such compute servers. Our experiments are done on the Stanford DASH, a distributed-memory cache-coherent multiprocessor. We show that for our multiprogramming workloads consisting of sequential jobs, the traditional Unix scheduling policy does very poorly. In contrast, a policy incorporating cluster and cache affinity along with a simple page-migration algorithm offers up to two-fold performance improvement. For our workloads consisting of multiple parallel applications, we compare space-sharing policies that divide the processors among the applications to time-slicing policies such as standard Unix or gang scheduling. We show that space-sharing policies can achieve better processor utilization due to the operating point effect, but time-slicing policies benefit strongly from user-level data distribution. Our initial experience with automatic page migration suggests that policies based only on TLB miss information can be quite effective, and useful for addressing the data distribution problems of space-sharing schedulers.","PeriodicalId":140481,"journal":{"name":"ASPLOS VI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 166

LCM: memory system support for parallel language implementation 内存系统支持并行语言实现

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195545

J. Larus, Brad Richards, Guhan Viswanathan

引用次数: 50

A technique for monitoring run-time dynamics of an operating system and a microprocessor executing user applications 一种监视操作系统和执行用户应用程序的微处理器运行时动态的技术

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195518

P. V. Argade, David K. Charles, C. Taylor

引用次数: 7

Resource allocation in a high clock rate microprocessor 高时钟速率微处理器的资源分配

ASPLOS VI Pub Date : 1994-11-01 DOI: 10.1145/195473.195510

M. Upton, T. Huff, T. Mudge, Richard B. Brown