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2012 IEEE International Conference on IC Design & Technology最新文献

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A new statistical setup and hold time definition 新的统计设置和保持时间定义
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232837
Xiaoliang Bai, P. Patel, Xiaonan Zhang
{"title":"A new statistical setup and hold time definition","authors":"Xiaoliang Bai, P. Patel, Xiaonan Zhang","doi":"10.1109/ICICDT.2012.6232837","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232837","url":null,"abstract":"Process variability becomes prominent for circuits using nanometer manufacturing technology. With aggressive voltage scaling, unexpected failures occur due to excessive timing variation. Yield, number of components, and process variability are intrinsically linked. In this paper, we study the setup and hold time definition, margin, and characterization methodology. A new statistical margin quantifying methodology, setup and hold time definition and characterization methodology are proposed.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance 一个0.32V, 55fJ / bit存取能量，CMOS 65nm位交错SRAM，具有辐射软误差容限
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232860
S. Clerc, F. Abouzeid, G. Gasiot, D. Gauthier, Dimitri Soussan, P. Roche
{"title":"A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance","authors":"S. Clerc, F. Abouzeid, G. Gasiot, D. Gauthier, Dimitri Soussan, P. Roche","doi":"10.1109/ICICDT.2012.6232860","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232860","url":null,"abstract":"A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling future medical appplications radiation reliability through bit-interleaving combined with error correcting code.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115036917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
“Phase-Change Memories for nano-scale technology and design” 纳米级技术与设计的相变存储器
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232857
F. Pellizzer, R. Bez
{"title":"“Phase-Change Memories for nano-scale technology and design”","authors":"F. Pellizzer, R. Bez","doi":"10.1109/ICICDT.2012.6232857","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232857","url":null,"abstract":"In this paper we will review the evolution of Phase-Change Memories (PCM) through the last decade, starting from the first electrical results on single cells and ending with the latest news of multi-Gb chips. Entering into the sub-30nm realm, PCM is demonstrating the capability to enter the broad memory market and to become a mainstream technology.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116829442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Lifetime prediction of channel hot carrier degradation in pMOSFETs separating NBTI component 分离NBTI元件的pmosfet通道热载流子退化寿命预测
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232842
Y. Mitani, S. Fukatsu, Daisuke Hagishima, K. Matsuzawa
{"title":"Lifetime prediction of channel hot carrier degradation in pMOSFETs separating NBTI component","authors":"Y. Mitani, S. Fukatsu, Daisuke Hagishima, K. Matsuzawa","doi":"10.1109/ICICDT.2012.6232842","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232842","url":null,"abstract":"Channel hot-carrier (CHC) degradation in p-channel MOSFETs essentially includes negative bias temperature instabilities (NBTI), which would lead to over-estimate the CHC degradation. Therefore, a separation of the BTI component from CHC degradation is necessary to predict device lifetime more accurately. In this study, a simple lifetime prediction method separating NBTI and CHC component from sequential CHC test (i.e. alternate stress and relax) data is proposed, focusing on the recovery phenomenon, which is a distinctive behavior of NBTI.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117293768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
BAW filters for ultra-low power narrow-band applications 超低功耗窄带应用的BAW滤波器
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232844
C. Bernier, J. David
{"title":"BAW filters for ultra-low power narrow-band applications","authors":"C. Bernier, J. David","doi":"10.1109/ICICDT.2012.6232844","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232844","url":null,"abstract":"This paper presents an original method for the design of Bulk Acoustic Wave (BAW) filters for a new class of applications: ultra-low-power, narrow-band RF filtering. To this end, a filter co-design methodology, based on existing BAW resonator technology and fabrication processes, is developed and the link between decreasing filter bandwidth and decreasing power consumption of the associated integrated circuit is demonstrated. Depending on required bandwidth, the power dissipation of the driving electronics can be reduced by large factors (10 to 40). Applications to High-IF receivers and Wake-up receivers are described.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132500190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy efficient design techniques for a digital signal processor 数字信号处理器的节能设计技术
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232843
P. Bassett, M. Saint-Laurent
{"title":"Energy efficient design techniques for a digital signal processor","authors":"P. Bassett, M. Saint-Laurent","doi":"10.1109/ICICDT.2012.6232843","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232843","url":null,"abstract":"Power is often cited as a key design metric for IC designs. However, for many integrated solutions a better measure of design quality is the overall energy efficiency of the design as low power does not always imply high energy efficiency. Many design tradeoffs must be made to balance the often-conflicting goals of high performance, low power, small area and high efficiency. This paper will use the context of a DSP core design to examine a small subset of the full range of design techniques that can be leveraged to directly impact the overall energy efficiency of a design: clock gating and structured clock trees, pulse latches and other multi-bit design structures, 8T vs 6T SRAM arrays, low-voltage retention vs power collapse, aggressive process-variation-aware frequency/voltage scaling with support for both run-fast-and-sleep and just-in-time execution modes, integrated power management solutions.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114596631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Minimum logic of guaranteed single soft error resilience based on group distance-two code 基于组距二码的保证单软错误弹性的最小逻辑
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232882
Bao Liu, Lu Wang
{"title":"Minimum logic of guaranteed single soft error resilience based on group distance-two code","authors":"Bao Liu, Lu Wang","doi":"10.1109/ICICDT.2012.6232882","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232882","url":null,"abstract":"Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. We construct minimum logic networks of guaranteed single soft error resilience by combining error detection and clock gating, and leveraging an existing fault-secure logic design technique, which is to construct group-sliced logic networks with outputs in group distance-two code. We propose two construction methods for minimum group distance-two code and minimum logic networks with outputs in a group distance-two code, respectively. Our experimental results show that we achieve guaranteed single soft error resilient logic networks of an average of 1.63× area, 1.63× critical path delay, and 2.17× power consumption, while DMR achieves an average of 2.12× area, 1.26× critical path delay, and 2.79× power consumption compared with the minimum area design.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125899540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world 超低功耗3D世界的新兴CMOS及超越CMOS技术
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232867
C. Kang, K. Ang, R. Hill, W. Loh, Jungwoo Oh, Rinus Lee, D. Gilmer, G. Bersuker, C. Hobbs, P. Kirsch, K. Hummler, S. Arkalgud, R. Jammy
{"title":"Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world","authors":"C. Kang, K. Ang, R. Hill, W. Loh, Jungwoo Oh, Rinus Lee, D. Gilmer, G. Bersuker, C. Hobbs, P. Kirsch, K. Hummler, S. Arkalgud, R. Jammy","doi":"10.1109/ICICDT.2012.6232867","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232867","url":null,"abstract":"We review various technology options for low power operation beyond the 14nm technology node with an insight into lower power solutions from both the technology and system perspectives.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126159813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memories 有史以来首款配备嵌入式纳米晶闪存和增强型 EEPROM 存储器的高性能、低功耗 32 位微控制器
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232858
J. Yater, S. Kang, C. Hong, B. Min, D. Kolar, K. Loiko, J. Shen, B. Winstead, H. Gasquet, S. Mohammed, A. Hardell, W. Malloch, B. Cook, R. Syzdek, A. Jarrar, J. Feddeler, K. Baker, K. Chang, S. Herrin, R. Parks, G. Chindalore
{"title":"First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memories","authors":"J. Yater, S. Kang, C. Hong, B. Min, D. Kolar, K. Loiko, J. Shen, B. Winstead, H. Gasquet, S. Mohammed, A. Hardell, W. Malloch, B. Cook, R. Syzdek, A. Jarrar, J. Feddeler, K. Baker, K. Chang, S. Herrin, R. Parks, G. Chindalore","doi":"10.1109/ICICDT.2012.6232858","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232858","url":null,"abstract":"We present the first-ever commercially available microcontroller families built with innovative split-gate based NOR flash memory that uses silicon nanocrystals as the storage medium. The 32-bit mixed-signal low-power Kinetis microcontroller families have nanocrystal based flash memories (referred to as TFS for `Thin Film Storage') with a wide range of array sizes from 32KB to 1MB. In addition, the unique capability of TFS has enabled inclusion of fully configurable embedded EEPROM functionality called `FlexMemory', which also manages wear leveling for high endurance. The TFS memory has been optimized to deliver read access time of <;30ns, fast source-side injection programming (10-20μs), fast tunnel erase into the gate (1-20ms), robust high temperature data retention before and after cycling, endurance of at least 10K cycles for flash and effective endurance up to 10M cycles in the EEPROM mode. In addition, the microcontroller core, analog and flash modules have been developed to deliver performance, reliability, and low-power operations across a temperature range of -40C to 105C and full operation down to 1.7V from a single power supply.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Temperature and process compensated clock generator using feedback TPC bias 使用反馈TPC偏置的温度和过程补偿时钟发生器
2012 IEEE International Conference on IC Design & Technology Pub Date : 2012-07-09 DOI: 10.1109/ICICDT.2012.6232863
Tzung-Je Lee, D. Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang
{"title":"Temperature and process compensated clock generator using feedback TPC bias","authors":"Tzung-Je Lee, D. Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang","doi":"10.1109/ICICDT.2012.6232863","DOIUrl":"https://doi.org/10.1109/ICICDT.2012.6232863","url":null,"abstract":"This paper proposes a temperature and process compensated clock generator using a feedback TPC (temperature and process compensation) bias circuit. With the proposed feedback TPC bias based on the OPA, MOS transistors and resistors, the BJT required in traditional bandgap bias circuit could be avoided. Thus, it is easy to be integrated with less area penalty. The proposed design is implemented using 0.25μm BCD process. According to the all-corners simulation results, the proposed clock generator processes the frequency diffusion error of 2.10% in the worst cases. Besides, the worst case duty cycle is simulated to be 48.93.%. The area of the chip is 0.1356 mm2.","PeriodicalId":135012,"journal":{"name":"2012 IEEE International Conference on IC Design & Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115030006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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