Integrated Circuits/Microchips最新文献

Tunnel Field Effect Transistors Based on Two-Dimensional Material Van-der-Waals Heterostructures 基于二维材料范德华异质结构的隧道场效应晶体管

Integrated Circuits/Microchips Pub Date : 2020-07-09 DOI: 10.5772/intechopen.93143

Jiang Cao

{"title":"Tunnel Field Effect Transistors Based on Two-Dimensional Material Van-der-Waals Heterostructures","authors":"Jiang Cao","doi":"10.5772/intechopen.93143","DOIUrl":"https://doi.org/10.5772/intechopen.93143","url":null,"abstract":"The successful isolation of graphene in 2004 has attracted great interest to search for potential applications of this unique material and other newborn mem-bers of the two-dimensional (2-D) family in electronics, optoelectronics, spintronics and other fields. Compared to graphene, the 2-D transition metal dichalcogenides (TMDs) have the advantage of being semiconductors, which would allow their use for logic devices. In the past decade, significant developments have been made in this area, where opportunities and challenges co-exist. Stacking different 2-D materials significantly increases the already considerable design space, especially when a type-II band alignment is obtained. This chapter will describe the recent progresses in the tunnel field-effect transistors based on 2-D TMD van-der-Waals heterostructure, which is one of the promising candidates for increasingly important low-power mobile computation applications. Due to their small size, such devices are intrinsically dominated by quantum effects. This requires the adoption of a fairly general theory of transport, such as the nonequilibrium Green's functions (NEGF) formalism, which is a method having been more-and-more used for the simulation of electron transport in nanostructures in recent years.","PeriodicalId":134829,"journal":{"name":"Integrated Circuits/Microchips","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127440170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tackling the Problem of Dangerous Radiation Levels with Organic Field-Effect Transistors 用有机场效应晶体管解决危险辐射水平问题

Integrated Circuits/Microchips Pub Date : 2020-06-16 DOI: 10.5772/intechopen.92808

I. Valitova, Z. Yi, Jonathan Sayago

引用次数: 0

Computationally Efficient Hybrid Interpolation and Baseline Restoration of the Brain-PET Pulses 脑- pet脉冲的高效混合插值与基线恢复

Integrated Circuits/Microchips Pub Date : 2020-05-07 DOI: 10.5772/intechopen.92193

S. Qaisar

{"title":"Computationally Efficient Hybrid Interpolation and Baseline Restoration of the Brain-PET Pulses","authors":"S. Qaisar","doi":"10.5772/intechopen.92193","DOIUrl":"https://doi.org/10.5772/intechopen.92193","url":null,"abstract":"The design and component level architectures of a novel offset compensated digital baseline restorer (BLR) and an original hybrid interpolator are described. It allows diminishing the effect of modifications occurring during the readout of Positron Emission Tomography (PET) pulses. Without treatment, such artifacts can result in a reduction in the scanner’s performance, such as its sensitivity and resolution. The BLR recompenses the offset of PET pulses. Afterward, the pertinent parts of these pulses are located. Onward, the located portion of the signal is resampled by using a hybrid interpolator. This is constructed by cascading an optimized weighted least-square interpolator (WLSI) and a Simplified Linear Interpolator (SLI). The regulation processes for the WLSI coefficients and evaluation of the BLR and the interpolator modules are presented. The proposed hybrid interpolator’s computational complexity is compared with classic counterparts. These modules are implemented in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) and synthesized on a Field Programmable Gate Array (FPGA). The functionality of the system is validated with an experimental setup. Results reveal notable computational gain along with adequate dynamic restitution of the bipolar offsets besides a useful and accurate improvement of the temporal resolution relative to the computationally complex conventional equivalents.","PeriodicalId":134829,"journal":{"name":"Integrated Circuits/Microchips","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128421408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory 区域高效自旋轨道转矩磁随机存取存储器

Integrated Circuits/Microchips Pub Date : 2020-04-15 DOI: 10.5772/intechopen.92120

Karim Ali

引用次数: 0

Ultra-Low-Voltage IC Design Methods 超低电压集成电路设计方法

Integrated Circuits/Microchips Pub Date : 2020-04-15 DOI: 10.5772/intechopen.91958

D. Arbet, L. Nagy, V. Stopjaková

{"title":"Ultra-Low-Voltage IC Design Methods","authors":"D. Arbet, L. Nagy, V. Stopjaková","doi":"10.5772/intechopen.91958","DOIUrl":"https://doi.org/10.5772/intechopen.91958","url":null,"abstract":"The emerging nanoscale technologies inherently offer transistors working with low voltage levels and are optimized for low-power operation. However, these technologies lack quality electronic components vital for reliable analog and/or mixed-signal design (e.g., resistor, capacitor, etc.) as they are predominantly used in high-performance digital designs. Moreover, the voltage headroom, ESD properties, the maximum current densities, parasitic effects, process fluctuations, aging effects, and many other parameters are superior in verified-by-time CMOS processes using planar transistors. This is the main reason, why low-voltage, low-power high-performance analog and mixed-signal circuits are still being designed in mature process nodes. In the proposed chapter, we bring an overview of main challenges and design techniques effectively applicable for ultra-low-voltage and low-power analog integrated circuits in nanoscale technologies. New design challenges and limitations linked with a low value of the supply voltage, the process fluctuation, device mismatch, and other effects are discussed. In the later part of the chapter, conventional and unconventional design techniques (bulk-driven approach, floating-gate, dynamic threshold, etc.) to design analog integrated circuits towards ultra-low-voltage systems and applications are described. Examples of ultra-low-voltage analog ICs blocks (an operational amplifier, a voltage comparator, a charge pump, etc.) designed in a standard CMOS technology using the unconventional design approach are presented.","PeriodicalId":134829,"journal":{"name":"Integrated Circuits/Microchips","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116451204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Crystal Polymorph Control for High-Performance Organic Field-Effect Transistors 高性能有机场效应晶体管晶体多晶控制

Integrated Circuits/Microchips Pub Date : 2020-04-08 DOI: 10.5772/intechopen.91905

Z. Fan, Hao‐Li Zhang

引用次数: 2

High Capacitance Dielectrics for Low Voltage Operated OFETs 低压ofet的高电容介电体

Integrated Circuits/Microchips Pub Date : 2020-03-20 DOI: 10.5772/intechopen.91772

N. Mohammadian, L. Majewski

引用次数: 1