ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)最新文献_第7页

A low-complexity VLSI architecture of multidimensional TCM decoder for ADSL ADSL多维TCM解码器的低复杂度VLSI结构

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.821005

Keum-Seok Lee, Jaeseok Kim

引用次数: 0

Analysis of sidewall films formed during Si etching with photoresist and nitride mask 光刻胶和氮化掩膜在Si蚀刻过程中形成的侧壁膜分析

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820856

So‐Young Nam, Sang‐Do Lee, J. Ha, Jin-Won Park

{"title":"Analysis of sidewall films formed during Si etching with photoresist and nitride mask","authors":"So‐Young Nam, Sang‐Do Lee, J. Ha, Jin-Won Park","doi":"10.1109/ICVC.1999.820856","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820856","url":null,"abstract":"The trench sidewall passivation films produced with photoresist (PR) mask and nitride mask were examined in two different etching systems of helicon and inductively coupled plasma (ICP) types. Compared to the trench profiles obtained from the helicon etching system, under the ICP etching system, the trench profiles were observed to be more tapered with thicker sidewall films. X-ray Photoelectron Spectroscopy (XPS) analysis results indicated that N/sub 2/ addition to Cl/sub 2//HBr/O/sub 2/ plasma induced the formation of Si-N bonds in the sidewall films in addition to Si-O and Si-Br bonds. Moreover, the sidewall films formed in Cl/sub 2//HBr/O/sub 2/ plasma showed higher oxygen intensities and higher binding energies compared to those formed in Cl/sub 2//HBr/N/sub 2//O/sub 2/ plasma. Nitride mask polymer films seem to be deposited thicker on the mask film for both helicon and ICP type etchers in comparison with the PR mask scheme. The oxygen component appeared more intensely on the silicon substrate in the helicon plasma etcher with the PR mask scheme, contrary to the nitride mask scheme. Cone-shaped microscopic Si defects were detected during Si trench etching regardless of etching system, but wafers etched with the nitride mask showed more defects than those etched with photoresist mask.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"21 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87281595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2048 complex point FFT processor for DAB systems 用于DAB系统的2048复点FFT处理器

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820915

Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi

引用次数: 5

A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method 一个4- 400mhz抖动抑制延迟锁定环分频方法

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820925

Y. Koo, Joonbae Park, Joonbae Park, Wonchan Kim

引用次数: 2

Silicon MOS memory with self-aligned quantum dot on narrow channel 窄通道自对准量子点硅MOS存储器

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820869

Sangyeon Han, T. Hwang, Hyungcheol Shin

引用次数: 0

A SPICE compatible single electron transistor (SET) transient model SPICE兼容单电子晶体管(SET)瞬态模型

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820945

Y. Yu, Y. Jung, S. Hwang, D. Ahn

引用次数: 1

Thermally stable W-bit line technology for ULSI device application 用于ULSI器件的热稳定w位线技术

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820975

Young Soo Kim, N. Park, J. K. Kim, S. Han, Kyungho Lee

引用次数: 0

High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme 采用动态超驱动和自适应传感方案的高速低摆接口电路

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820940

Chang-Ki Kwon, KwangMyoung Rho, Kwyro Lee

引用次数: 13

Enhancing uniformity of borderless via resistance by HDP oxide technology 利用HDP氧化技术提高无边界通孔电阻的均匀性

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820962

Yong-Sik Jung, C. Kim, J. Kim, J. Han, Y. Seo, Y. Jeon

{"title":"Enhancing uniformity of borderless via resistance by HDP oxide technology","authors":"Yong-Sik Jung, C. Kim, J. Kim, J. Han, Y. Seo, Y. Jeon","doi":"10.1109/ICVC.1999.820962","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820962","url":null,"abstract":"This paper describes part of the technology of a five level metal interconnection method for a 25C07 (gate CD: 0.25 /spl mu/m, metal1 pitch design rule: 0.76 /spl mu/m) CMOS device. In order to achieve the stable interconnection of metal lines, first we should open the via holes very clearly and uniformly through a via patterning/etching process, and not only the strong barrier metal (Ti/TiN) property for surrounding the via hole, especially the bottom corner, but also the proper W filling in the via hole, is required. Another important factor is the Intermetal Dielectric Material (IMD). When we have no room (almost zero) of the via hole to endlap the bottom metal, the IMD material can give effect to the via resistance. The objective of this experiment is to look at the via resistance difference in the zig-zag test pattern (via CD: 0.33 /spl mu/m, via endlap to bottom metal: 0.1 /spl mu/m, via sidelap to bottom metal: 0.02 /spl mu/m, metal width/space: 0.4 /spl mu/m/0.36 /spl mu/m) due to the IMD materials (HDP USG vs. SOG) and, finally, compare the device yield. High Density Plasma CVD (HDP USG) and SOG (Spin On Glass) were performed as a split corner of IMD layer deposition. Every process step, from pad oxidation to passivation, except IMD layer deposition( HDP CVD and. SOG coating and cure), was done simultaneously under the completely same condition. In this work, we monitored the \"process in line data\" such as global planarization of post IMD CMP and via photo CD/etch CD to correlate the electrical via resistance data with \"process in line data\".","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"23 1","pages":"452-455"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78175742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimum barrier layer for Al-PMD (preferential metal deposition) process Al-PMD(优先金属沉积)工艺的最佳阻挡层

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820884

B. Kim, Jong Myeong Lee, Y. Chae, S. Kang, G. Choi, Y. Park, Sang In Lee

引用次数: 0