Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools最新文献

A Bank-Wise DRAM Power Model for System Simulations 用于系统仿真的银行智能DRAM功耗模型

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 2017-01-23 DOI: 10.1145/3023973.3023978

Deepak M. Mathew, Éder F. Zulian, Subash Kannoth, Matthias Jung, C. Weis, N. Wehn

引用次数: 14

Throughput Propagation in Constraint-Based Design Space Exploration for Mixed-Criticality Systems 基于约束的混合临界系统设计空间探索中的吞吐量传播

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 2017-01-23 DOI: 10.1145/3023973.3023977

Kathrin Rosvall, N. Khalilzad, George Ungureanu, I. Sander

{"title":"Throughput Propagation in Constraint-Based Design Space Exploration for Mixed-Criticality Systems","authors":"Kathrin Rosvall, N. Khalilzad, George Ungureanu, I. Sander","doi":"10.1145/3023973.3023977","DOIUrl":"https://doi.org/10.1145/3023973.3023977","url":null,"abstract":"When designing complex mixed-critical systems on multiprocessor platforms, a huge number of design alternatives has to be evaluated. Therefore, there is a need for tools which systematically find and analyze the ample alternatives and identify solutions that satisfy the design constraints. The recently proposed design space exploration (DSE) tool DeSyDe uses constraint programming (CP) to find implementations with performance guarantees for multiple applications with potentially mixed-critical design constraints on a shared platform. A key component of the DeSyDe tool is its throughput analysis component, called a throughput propagator in the context of CP. The throughput propagator guides the exploration by evaluating each design decision and is therefore executed excessively throughout the exploration. This paper presents two throughput propagators based on different analysis methods for DeSyDe. Their performance is evaluated in a range of experiments with six different application graphs, heterogeneous platform models and mixed-critical design constraints. The results suggest that the MCR throughput propagator is more efficient.","PeriodicalId":131314,"journal":{"name":"Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132555784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication 基于状态的共享内存通信mpsoc上fsm - sadfg的RT分析

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 2017-01-23 DOI: 10.1145/3023973.3023979

R. Stemmer, Maher Fakih, Kim Grüttner, W. Nebel

引用次数: 1

Early Stage Interference Checking for Automatic Design Space Exploration of Mixed Critical Systems 混合临界系统自动设计空间探索的早期干扰检测

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 2017-01-23 DOI: 10.1145/3023973.3023976

E. Vitali, G. Palermo

{"title":"Early Stage Interference Checking for Automatic Design Space Exploration of Mixed Critical Systems","authors":"E. Vitali, G. Palermo","doi":"10.1145/3023973.3023976","DOIUrl":"https://doi.org/10.1145/3023973.3023976","url":null,"abstract":"Significant improvements have been made to support the design of mixed-critical systems by developing predictable computing platforms and mechanisms for temporal and spatial segregation between applications of different criticalities sharing the same computing platform. However the design of such Multi-Processor System-on-Chips (MPSoCs) supporting mixed-critical applications needs methodologies and tools to improve the analyzability regarding system configuration and application mapping. Among the required techniques, in this work we focus on the possibility to identify, at the early stages of the design, possible unexpected interactions among tasks relying to different criticalities. In particular, we introduce a dependency check tool to automatically find possible interactions between tasks during the design of a mixed critical embedded system. The proposed tool searches on an abstract system model for the possible interactions, thus helping pruning all the design configurations not respecting the considered criticality constraints. In this way the methodology can be used to speed-up the following design space exploration phase based on functional models (e.g. simulation based) avoiding costly evaluations. Even if the methodology is general, up to now only the timing aspect has been fully modeled and developed, so this paper will focus on this aspect.","PeriodicalId":131314,"journal":{"name":"Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Adaptive Cache Warming for Faster Simulations 自适应缓存升温更快的模拟

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 2017-01-23 DOI: 10.1145/3023973.3023974

Gustaf Borgström, Andreas Sembrant, D. Black-Schaffer

{"title":"Adaptive Cache Warming for Faster Simulations","authors":"Gustaf Borgström, Andreas Sembrant, D. Black-Schaffer","doi":"10.1145/3023973.3023974","DOIUrl":"https://doi.org/10.1145/3023973.3023974","url":null,"abstract":"The use of hardware-based virtualization allows modern simulators to very quickly fast-forward between sample points and regions of interest. This dramatically reduces the simulation time compared to traditional functional forwarding. However, as the fast-forwarding takes place through virtualized execution on the native hardware, it is unable to warm simulated structures, such as caches. As a result, sampled simulations taking advantage of virtualization for fast-forwarding find their execution time dominated by functional warming. To address the cost of warming, we present Adaptive Cache Warming (ACW), a new fast method that determines how much warming each sample/phase/application needs. ACW takes advantage of the virtualization-based fast-forwarding to search for the minimum warming time required during simulation. To determine when the cache is sufficiently warm, ACW uses heuristics based on the last-level cache's cold-set misses. Our results show that typical practice of conservatively warming last-level caches for around 100M instructions is a vast overkill for nearly all checkpoints. By using ACW, we can adapt the warming per-sample and speedup the simulation by 92--103× on average (512× speedup maximum) depending on cache size (2-32MB).","PeriodicalId":131314,"journal":{"name":"Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models 使用并行系统和处理器睡眠模型加速MPSoC仿真

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 2017-01-23 DOI: 10.1145/3023973.3023975

Jan Weinstock, R. Leupers, G. Ascheid

引用次数: 1

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools 第九届快速仿真与性能评估研讨会论文集:方法与工具

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools Pub Date : 1900-01-01 DOI: 10.1145/3023973

引用次数: 0