Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models

Abstract

High simulation speed is always a concern for developers of virtual platforms, especially given the ever increasing number of processors in modern designs. On the one hand, parallel simulation has appeared as a promising candidate, but has yet to be fully studied in realistic virtual platforms such as those deployed by the industry today. On the other hand, omission of unneeded simulation details, such as skipping simulation of processors in idle or low-power states, also improves performance. This work studies both approaches combined in a realistic virtual platform, achieving average performance gains of 3.2x over sequential simulation.