A Bank-Wise DRAM Power Model for System Simulations

Abstract

DRAM devices contribute significantly to the power consumption of today's computing systems. As the DRAM banks are getting denser, bank-wise power contribution is becoming more and more significant in modern DRAM devices. Therefore, DDR3 and LPDDR3/4 devices support Partial Array Self Refresh (PASR), while the latter and High Bandwidth Memory (HBM) provide additionally Per-Bank Refresh. To evaluate the benefits of these new sophisticated features in design space explorations, it is essential to have an accurate and fast Bank-Wise DRAM power model, which can be easily integrated into system level simulators. To the best of our knowledge, there exists no DRAM power model, which supports the aforementioned features. In this work, we present the fundamental equations for modeling bank-wise DRAM power. This model supports PASR and Per-Bank Refresh and is calibrated with measurements from various DRAM devices to improve the accuracy instead of using pessimistic datasheet values.