{"title":"A neuromorphic paradigm for extrinsically evolved hybrid analog/digital device controllers: initial explorations","authors":"J. Gallagher","doi":"10.1109/EH.2001.937947","DOIUrl":"https://doi.org/10.1109/EH.2001.937947","url":null,"abstract":"This paper argues that the continuous time recurrent neural network (CTRNN) provides a particularly attractive paradigm for the extrinsic evolution of analog device controllers. The paper begins with a discussion of motivations and difficulties faced in evolving electrical circuits and then illustrates how some of these difficulties have been successfully addressed in the context of evolved CTRNNs. This paper provides a presentation of a new, hardware friendly, CTRNN formulation as well as some preliminary experimental results demonstrating that practical devices can be evolved under the new model. Finally, the paper will conclude with a discussion of open issues and a summary of current plans to close those gaps.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126079073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Methods for evolving robust distributed robot control software: coevolutionary and single population techniques","authors":"B. Dolin, F. H. Bennett, E. Rieffel","doi":"10.1109/EH.2001.937943","DOIUrl":"https://doi.org/10.1109/EH.2001.937943","url":null,"abstract":"Previous work on evolving distributed control software for modular robots has resulted in solutions that do not generalize well to unseen test cases. In this work, we seek general solutions to an entire space of test cases. Each test case is a specific world configuration with a passage through which the modular robot must move. The space of test cases is extremely large, so a given training set can only be a sparse sample of this space. We look at several approaches for dealing with the problem of determining an effective training set: using a fixed set throughout a run, sampling randomly at each generation, and using coevolutionary approaches to evolve a population of test worlds. For this problem, random sampling outperformed the fixed sampling technique and did at least as well as the coevolutionary techniques we considered.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114940192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolutionary design and adaptation of digital filters within an embedded fault tolerant hardware platform","authors":"B. Hounsell, T. Arslan","doi":"10.1109/EH.2001.937954","DOIUrl":"https://doi.org/10.1109/EH.2001.937954","url":null,"abstract":"Finite impulse response filters (FIRs) are crucial device for robust data communication and manipulation. Multiplierless filters have been shown to produce high performance systems with fast signal processing and reduced area. Furthermore, the distributed architecture inherent in multiplierless filters makes it a suitable candidate for fault tolerant design. Alternative approaches to the design of fault tolerant systems have been proposed using evolutionary algorithms (EAs) and the concept of evolvable hardware (EHW). This paper presents an evolvable hardware platform for the automated design and adaptation of multiplierless digital filters. Filters are realised within a dedicated programmable logic array (PLA). The platform employs a genetic algorithm to autonomously configure the PLA for a give set of coefficients. The ability of the platform to adapt to increasing numbers of faults was investigated through the \"evolution\" of a 31-tap low-pass FIR filter. Results show that the functionality of filters evolved on the PLA was maintained despite an increasing number of faults covering up to 25% of the PLA area. Additionally, three PLA initialisation methods were investigated to ascertain which produced the fastest fault recovery times. It was shown that seeding a population of random configuration-strings with the best configuration currently obtained resulted in a 6 fold increase in fault recovery speed over other methods investigated.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130058555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The ispPAC family of reconfigurable analog circuits","authors":"E. Ramsden","doi":"10.1109/EH.2001.937960","DOIUrl":"https://doi.org/10.1109/EH.2001.937960","url":null,"abstract":"The Lattice Semiconductor ispPAC series of programmable analog circuits are among the most recent commercially available programmable analog circuits. A brief overview of the existing members of the ispPAC family is presented, as are descriptions of applications for programmable analog integrated circuits. A discussion of some of the ways in which programmable analog integrated circuits can be used is also presented.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131132129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolutionary strategies and intrinsic fault tolerance","authors":"A. Tyrrell, G. Hollingworth, S. Smith","doi":"10.1109/EH.2001.937951","DOIUrl":"https://doi.org/10.1109/EH.2001.937951","url":null,"abstract":"Redundancy is a critical component to the design of fault tolerant systems; both hardware and software. This paper explores the possibilities of using evolutionary techniques to first produce a processing system that will perform a required function, and then consider its applicability for producing useful redundancy that can be made use of in the presence of faults, ie is it fault tolerant? Results obtained using evolutionary strategies to automatically create redundancy as part of the \"design\" process are given. The experiments are undertaken on a Virtex FPGA with intrinsic evolution taking place. The results show that not only does the evolutionary process produce useful redundancy, it is also possible to reconfigure the system in real-time on the Virtex device.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121280981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of a breeder genetic algorithm for system identification in an adaptive finite impulse response filter","authors":"O. Castillo, P. Melin, O. Montiel, R. Sepúlveda","doi":"10.1109/EH.2001.937956","DOIUrl":"https://doi.org/10.1109/EH.2001.937956","url":null,"abstract":"We describe in this paper the application of a breeder genetic algorithm to the problem of parameter identification for an adaptive finite impulse filter. A breeder genetic algorithm was needed due to the epistiasis phenomena, which is present for this type of adaptive filter. The results of the genetic algorithm were compared to the traditional statistical method and, we found that the breeder genetic algorithm was clearly superior (in accuracy) in most of the cases. However, the statistical least mean squares method is faster then the genetic algorithm. For this reason we suggest using the genetic algorithm for off-line adaptation. Ay hybrid method combining the advantages of both methods is proposed for real world applications.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Porter, M. Gokhale, N. Harvey, S. Perkins, A. Young
{"title":"Evolving network architectures with custom computers for multi-spectral feature identification","authors":"R. Porter, M. Gokhale, N. Harvey, S. Perkins, A. Young","doi":"10.1109/EH.2001.937970","DOIUrl":"https://doi.org/10.1109/EH.2001.937970","url":null,"abstract":"This paper investigates the design of evolvable FPGA circuits where the design space is severely constrained to an interconnected network of meaningful high-level operators. The specific design domain is image processing, especially pattern recognition in remotely sensed images. Preliminary experiments are reported that compare neural networks with a recently introduced variant known as morphological networks. A novel network node is then presented that is particularly suited to the problem of pattern recognition in multi-spectral data sets. More specifically, the node can exploit both spectral and spatial information, and implements both feature extraction and classification components of a typical image processing pipeline. Once trained, the network can be applied to large image data sets, for at the sensor to extract features of interest with two orders of magnitude speed-up compared to software implementations.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125991463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bridging the genotype-phenotype mapping for digital FPGAs","authors":"P. Haddow, G. Tufte","doi":"10.1109/EH.2001.937952","DOIUrl":"https://doi.org/10.1109/EH.2001.937952","url":null,"abstract":"To solve the genome complexity issue and enable evolution of large complex circuits, the need to move away from a one-to-one genotype/phenotype mapping is becoming generally accepted. This involves development of new forms of representation with features such as growth. Shrinking the size of the genotype in effect moves complexity from the genotype representation to the genotype/phenotype mapping. The field of digital evolvable hardware is relatively young but already researchers have not only had to move through different technology platforms i.e. 6200, 4000 and Virtex series, but also evolution friendly features have disappeared. A mass produced evolution friendly reconfigurable platform is not likely to be ahead of us and a newer technology more evolution friendly than traditional reconfigurable platforms is not around the corner. To be able to reuse results and lessons learned from today's technology on tomorrow's technology and exploit the power of evolution, one solution is to provide a virtual evolution friendly reconfigurable platform which may be mapped onto a given technology. We propose a two stage genotype/phenotype mapping using our virtual evolvable hardware FPGA us the bridge. The two stages simplify the genotype/phenotype transition at the same time as the virtual evolvable hardware FPGA bridge provides a more evolution friendly platform, further reducing the complexity of the genotype representation.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125672681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. C. Santini, M. Pacheco, M. Vellasco, M. H. Szwarcman, R. Zebulum
{"title":"PAMA-programmable analog multiplexer array","authors":"C. C. Santini, M. Pacheco, M. Vellasco, M. H. Szwarcman, R. Zebulum","doi":"10.1109/EH.2001.937945","DOIUrl":"https://doi.org/10.1109/EH.2001.937945","url":null,"abstract":"This paper describes PAMA (Programmable Analog Multiplexer Array), a reconfigurable platform for exploring the intrinsic evolution of analog hardware. The reconfigurable platform consists of integrated circuits whose internal connections can be programmed by the user. The platform characteristics are discussed, such as it's flexibility, once the discrete components can be of any type (fine or coarse grained). This latest PAMA version described in this paper presents some advantages concerning the prototype platform which was first used to intrinsically evolve circuits. The Analog Reconfigurable Circuit allows more component terminals, allowing the evolution of a great number of circuits and the circuit evaluation time has decreased considerably.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131965159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asynchronous embryonics","authors":"Alexander H. Jackson, A. Tyrrell","doi":"10.1109/EH.2001.937963","DOIUrl":"https://doi.org/10.1109/EH.2001.937963","url":null,"abstract":"As embryonic arrays take inspiration from nature they display biological properties, namely complex structure and fault-tolerance. However, they have yet to take advantage of a further biological feature at a fundamental level; asynchronous operation. In addition to the benefits normally associated with asynchronous digital design, such as intrinsic power management, two areas in which embryonic arrays could benefit are scalability and reliability. This paper gives an overview of embryonic systems and a pertinent asynchronous methodology, that of macromodules. It is shown that a macromodule approach allows the implementation of asynchronous circuits on Xilinx Virtex FPGAs using only the standard design tools. A preliminary VHDL simulation illustrates the operation of an asynchronous embryonic array. Although mentioned, little detail of the reconfiguration scheme is given for brevity. This simulation brings truly asynchronous embryonic circuits a step closer.","PeriodicalId":130694,"journal":{"name":"Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123975212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}