{"title":"Efficient On-line Schedulability Test for Feedback Scheduling of Soft Real-Time Tasks under Fixed-Priority","authors":"Rodrigo M. Santos, G. Lipari, Enrico Bini","doi":"10.1109/RTAS.2008.26","DOIUrl":"https://doi.org/10.1109/RTAS.2008.26","url":null,"abstract":"When dealing with soft real-time tasks with highly variable execution times in open systems, an approach that is becoming popular is to use feedback scheduling techniques to dynamically adapt the bandwidth reserved to each task. According to this model, each task is assigned an adaptive reservation, with a variable budget and a constant period. The response times of the jobs of the task are monitored and if different from expected (i.e. much larger or much shorter than the task relative deadline), a feedback control law adjusts the reservation budget accordingly. However, when the feedback law algorithm demands an increase of the reservation budget, the system must run a schedulability test to check if there is enough spare bandwidth to accommodate such increase. The schedulability test must be very efficient, as it may be performed at each budget update, i.e. potentially at each instance of a task. In this paper, we tackle the problem of performing an efficient on-line schedulability test for Resource Reservation systems implemented through the Sporadic Server on Fixed Priority scheduling. We propose five different tests with different complexity and performance. In particular, we propose a novel on-line test, called Spare Pot algorithm which shows a good cost/performance ratio.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133989860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Buffer Capacity Computation for Throughput Constrained Streaming Applications with Data-Dependent Inter-Task Communication","authors":"M. Wiggers, M. Bekooij, G. Smit","doi":"10.1109/RTAS.2008.10","DOIUrl":"https://doi.org/10.1109/RTAS.2008.10","url":null,"abstract":"Streaming applications are often implemented as task graphs, in which data is communicated from task to task over buffers. Currently, techniques exist to compute buffer capacities that guarantee satisfaction of the throughput constraint if the amount of data produced and consumed by the tasks is known at design-time. However, applications such as audio and video decoders have tasks that produce and consume an amount of data that depends on the decoded stream. This paper introduces a dataflow model that allows for data-dependent communication, together with an algorithm that computes buffer capacities that guarantee satisfaction of a throughput constraint. The applicability of this algorithm is demonstrated by computing buffer capacities for an H.263 video decoder.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Regular Specifications of Resource Requirements for Embedded Control Software","authors":"R. Alur, Gera Weiss","doi":"10.1109/RTAS.2008.13","DOIUrl":"https://doi.org/10.1109/RTAS.2008.13","url":null,"abstract":"For embedded control systems, a schedule for the allocation of resources to a software component can be described by an infinite word whose ith symbol models the resources used at the ith sampling interval. Dependency of performance on schedules can be formally modeled by an automaton (omega-regular language) which captures all the schedules that keep the system within performance requirements. We show how such an automaton is constructed for linear control designs and exponential stability or settling time performance requirements. Then, we explore the use of the automaton for online scheduling and for schedulability analysis. As a case study, we examine how this approach can be applied for the LQG control design. We demonstrate, by examples, that online schedulers can be used to guarantee performance in worst-case condition together with good performance in normal conditions. We also provide examples of schedulability analysis.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TOSSTI: Saving Time and Energy in TinyOS with Software Thread Integration","authors":"Zane D. Purvis, A. Dean","doi":"10.1109/RTAS.2008.38","DOIUrl":"https://doi.org/10.1109/RTAS.2008.38","url":null,"abstract":"Many wireless sensor nodes (motes) interface with slow peripheral devices, requiring the processor to wait. These delays waste time, energy and power, which are valuable but limited resources on many motes. This paper presents techniques to use software thread integration (STI) in TinyOS applications to recover the idle time for useful processing. We modify the TOS scheduler to support the selection and execution of integrated threads. We analyze the impact of integration on task response time. We demonstrate these methods by applying them to a microphone array sampling application to save computation time and energy. We find that the integrated tasks finish 17.7% faster, reducing application active time (and hence application energy) by 6.3%.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115889332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Natale, Guoqiang Wang, A. Sangiovanni-Vincentelli
{"title":"Optimizing the Implementation of Communication in Synchronous Reactive Models","authors":"M. Natale, Guoqiang Wang, A. Sangiovanni-Vincentelli","doi":"10.1109/RTAS.2008.23","DOIUrl":"https://doi.org/10.1109/RTAS.2008.23","url":null,"abstract":"A fundamental asset of a model-based development process is the capability of providing an automatic implementation of the model that preserves its semantics and, at the same time, makes an efficient use of the resources of the execution platform. The implementation of communication between functional blocks in a synchronous reactive model requires buffering schemes and access procedures at the kernel level. Previous research has provided two competing proposals for the sizing of the communication buffer. We demonstrate how it is possible to leverage task timing information to obtain tighter bounds for the case of sporadic tasks or periodic tasks with unknown activation phase, and we propose an approach that applies to a more general model. Furthermore, we provide the description of the data structures and constant-time access procedures for writer and reader tasks, and an implementation compliant with the OSEK OS standard.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124801901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Harmon, Martin Schoeberl, R. Kirner, R. Klefstad
{"title":"A Modular Worst-case Execution Time Analysis Tool for Java Processors","authors":"T. Harmon, Martin Schoeberl, R. Kirner, R. Klefstad","doi":"10.1109/RTAS.2008.34","DOIUrl":"https://doi.org/10.1109/RTAS.2008.34","url":null,"abstract":"Recent technologies such as the real-time specification for Java promise to bring Java's advantages to real-time systems. While these technologies have made Java more predictable, they lack a crucial element: support for determining the worst-case execution time (WCET). Without knowledge of WCET, the correct temporal behavior of a Java program cannot be guaranteed. Although considerable research has been applied to the theory of WCET analysis, implementations are much less common, particularly for Java. Recognizing this deficiency, we have created an open-source, extensible tool that supports WCET analysis of Java programs. Designed for flexibility, it is built around a plug- in model that allows features to be incorporated as needed. Users can plug in various processor models, loop bound detectors, and WCET analysis algorithms without having to understand or alter the tool's internals.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126019839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jianliang Yi, Honguk Woo, J. Browne, A. Mok, Fei Xie, E. Atkins, Chan-Gun Lee
{"title":"Incorporating Resource Safety Verification to Executable Model-based Development for Embedded Systems","authors":"Jianliang Yi, Honguk Woo, J. Browne, A. Mok, Fei Xie, E. Atkins, Chan-Gun Lee","doi":"10.1109/RTAS.2008.28","DOIUrl":"https://doi.org/10.1109/RTAS.2008.28","url":null,"abstract":"This paper formulates and illustrates the integration of resource safety verification into a design methodology for development of verified and robust real-time embedded systems. Resource-related concerns are not closely linked with current xUML model-based software development although they are critical for embedded systems. We describe how to integrate resource analysis techniques into the early phase of an xUML-based development cycle. Our hybrid framework for resource safety verification combines static resource analysis and runtime monitoring. A case study based on an embedded controller for satellite simulation, TableSat, illustrates the benefits obtained by incorporating resource verification into design and combining static analysis and runtime monitoring.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114638264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modular Code Generation from Triggered and Timed Block Diagrams","authors":"Roberto Lublinerman, S. Tripakis","doi":"10.1109/RTAS.2008.12","DOIUrl":"https://doi.org/10.1109/RTAS.2008.12","url":null,"abstract":"In previous work we have shown how modular code can be automatically generated from a synchronous block diagram notation where all blocks fire at all times. Here, we extend this work to triggered and timed diagrams, where some blocks fire only when their trigger is true, or at statically specified times. We show that, although triggers can be eliminated, this is not desirable since it destroys modularity and may also result in rejecting some diagrams that could be accepted. To avoid this we propose a modular code generation method that directly accounts for triggers. We also propose methods specialized to timed diagrams. Although timed diagrams are special cases of triggered diagrams, treating them directly allows us to obtain efficient code. We achieve this by enriching the interface of a macro block with firing time information and using this information to avoid firing the block unnecessarily. Existing firing time representations are generally conservative, in the sense that they cannot represent the exact set of firing times of a macro block, but a super-set. To remedy this, we devise a novel and accurate (exact) representation. This representation uses finite automata and is amenable to algebraic manipulation and generation of efficient code.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126482637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver","authors":"Mingxuan Yuan, Xiuqiang He, Z. Gu","doi":"10.1109/RTAS.2008.39","DOIUrl":"https://doi.org/10.1109/RTAS.2008.39","url":null,"abstract":"FPGAs are often used together with a CPU as hardware accelerators. A runtime reconfigurable FPGA allows part of the FPGA area to be reconfigured while the remainder continues to operate without interruption, so that hardware tasks can be placed and removed dynamically at runtime. In this paper, we formulate and solve the problem of optimal hardware/software partitioning and static task scheduling for a hybrid FPGA/CPU device, with the optimization objective of minimizing the total schedule length, in the framework of satisfiability modulo theories (SMT) with linear integer arithmetic.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129704598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures","authors":"J. Whitham, N. Audsley","doi":"10.1109/RTAS.2008.11","DOIUrl":"https://doi.org/10.1109/RTAS.2008.11","url":null,"abstract":"Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues posed by caches. Trace scratchpads extend this paradigm with support for instruction level parallelism (ILP) while preserving simplicity of WCET analysis. In this paper, we demonstrate trace scratchpads using the MCGREP-2 CPU architecture. We provide a sample algorithm to automatically reduce the WCET of a program using a trace scratchpad, and compare the results with the use of an instruction scratchpad. We find that the two types of scratchpad are best used together. Instruction scratchpads provide excellent WCET improvements at low cost, but trace scratchpads reduce WCET further by optimizing worst case (WC) paths and exploiting ILP across basic block boundaries. Using our experimental implementation, we have observed WCET improvements over an instruction scratchpad of up to 149% with some Malardalen WCET benchmarks.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125766163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}