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2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)最新文献

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Untruth, falsity and non-deterministic semantics 不真实，虚假和非确定性语义
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00022
Hitoshi Omori, Daniel Skurt
{"title":"Untruth, falsity and non-deterministic semantics","authors":"Hitoshi Omori, Daniel Skurt","doi":"10.1109/ISMVL51352.2021.00022","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00022","url":null,"abstract":"Non-deterministic semantics is known as an elegant and powerful framework that generalizes many-valued (or multiple-valued) semantics. In this paper, we focus on a subsystem of classical propositional logic - CLoN, obtained by removing all the axioms for negation, while keeping negation in the language. Given that there are two non-deterministic semantics for this system in the literature, we aim to address the question about the exact difference between these two semantics. In brief, the two different readings of the value 0 in the semantics for classical propositional logic will play an important role for that matter.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122182293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quantales in Circuit Design 电路设计中的量子
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00016
P. Eklund
{"title":"Quantales in Circuit Design","authors":"P. Eklund","doi":"10.1109/ISMVL51352.2021.00016","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00016","url":null,"abstract":"Circuit design requires robustness to counteract undesirable variability, as typically seen e.g. in magnetic memory devices. Approximation to discrete structures is needed so that, on the one hand, the size of the structure is not too small where richer algebraic structures cannot be integrated, and, on the other hand, not too large so that variability makes practical application unfeasible.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132824446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories 一种实用的浮动门存储器第四纪FPGA
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00036
Ayokunle Fadamiro, Pouyan Rezaie, S. Millican, Christoper B. Harris
{"title":"A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories","authors":"Ayokunle Fadamiro, Pouyan Rezaie, S. Millican, Christoper B. Harris","doi":"10.1109/ISMVL51352.2021.00036","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00036","url":null,"abstract":"Consumer demands are outgrowing the benefits of technology scaling, especially for binary circuits. Previous studies proposed multi-valued logic (MVL) architectures, but these architectures use non-standard fabrication techniques and optimistic performance analysis. This study presents a new quaternary FPGA (QFPGA) architecture based on floating-gate memories which can be manufactured through standard CMOS fabrication. When simulated with open-source FinFET SPICE models, artifacts suggest competitive delay and power performance compared to equivalent binary circuits and other QFPGA architectures, and projection onto benchmark circuits predict additional performance improvements of up to 55% less area and one-third power reduction.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"573 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Lessons Learnt in the Implementation of Quantum Circuit Simulation Using Decision Diagrams 使用决策图实现量子电路仿真的经验教训
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00024
Thomas Grurl, Jürgen Fuß, R. Wille
{"title":"Lessons Learnt in the Implementation of Quantum Circuit Simulation Using Decision Diagrams","authors":"Thomas Grurl, Jürgen Fuß, R. Wille","doi":"10.1109/ISMVL51352.2021.00024","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00024","url":null,"abstract":"Decision diagrams have shown to be a suitable data-structure for tackling the complexity of the quantum world. Accordingly, there has been a lot of research on how to improve their efficiency for quantum circuit simulation as well as broadening their scope. However, there are several smaller yet still interesting aspects that emerge when (re-)implementing corresponding approaches. In this work, we cover these aspects, illustrate them with examples, back them by further experiments, and derive corresponding learnt lessons from these considerations. This eventually gives more detailed insights into the implementation of quantum circuit simulation based on decision diagrams and eventually offers some interesting lessons learnt that may help to use those implementations in a more effective fashion and/or to develop further improvements upon them.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122269045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantum Algorithm for Machine Learning and Circuit Design Based on Optimization of Ternary - Input, Binary-Output Kronecker-Reed-Muller Forms 基于三输入二输出Kronecker-Reed-Muller形式优化的机器学习和电路设计的量子算法
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00029
Ma Bao, Cole Powers, M. Perkowski
{"title":"Quantum Algorithm for Machine Learning and Circuit Design Based on Optimization of Ternary - Input, Binary-Output Kronecker-Reed-Muller Forms","authors":"Ma Bao, Cole Powers, M. Perkowski","doi":"10.1109/ISMVL51352.2021.00029","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00029","url":null,"abstract":"Paper introduces a new spectral expansion of ternary-input binary-output functions that generalizes the binary Kronecker-Reed-Muller forms. Two binary Davio Expansions are generalized to 27 Ternary-Input Davio Expansions. New KRM spectrum has 28n expansions for $n$ ternary variables. By creating an oracle for this problem we generalize the quantum Grover-based algorithms presented for the binary FPRM and KRM forms in the past. Because the method finds solutions also to incompletely specified functions, it can be used to both quantum circuit design and Machine Learning classifier design.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125191017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Binary, Multi-Valued and Quantum Board and Computer Games to Teach Synthesis of Classical and Quantum Logic Circuits 二进制，多值和量子棋盘和计算机游戏，教授经典和量子逻辑电路的综合
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00025
M. Perkowski, Kyle Liu
{"title":"Binary, Multi-Valued and Quantum Board and Computer Games to Teach Synthesis of Classical and Quantum Logic Circuits","authors":"M. Perkowski, Kyle Liu","doi":"10.1109/ISMVL51352.2021.00025","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00025","url":null,"abstract":"The paper presents a new didactic concept of teaching synthesis and optimization of classical, multi-valued, and quantum circuits by playing games. New types of classical and quantum, board and computer games are introduced. We were able to use the concepts from this paper to successfully teach middle and high school students about synthesis of several types of circuits. Concepts of Interpretation of Quantum Mechanics are also illustrated. The goal is not only to teach how to design circuits but also how to create new algorithms. Some concepts of Machine Learning are also taught through these games.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A New Approach to Machine Learning Based on Functional Decomposition of Multi -Valued Functions 基于多值函数泛函分解的机器学习新方法
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00030
Saad Al-Askaar, M. Perkowski
{"title":"A New Approach to Machine Learning Based on Functional Decomposition of Multi -Valued Functions","authors":"Saad Al-Askaar, M. Perkowski","doi":"10.1109/ISMVL51352.2021.00030","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00030","url":null,"abstract":"This paper presents a novel design of a hardware classifier based on combining modified Ashenhurst-Curtis Decomposition and modified multiplexer-based synthesis. The PSUD classifier brings three new contributions: an approach to solve the column multiplicity problem for both types of decomposition, the way how the multiple-valued variables are encoded and used, and a modification of the Ashenhurst-Curtis Decomposition. One of the biggest challenges in Boolean function decomposition is the variable partitioning problem. Thus, we introduce a new representation of two combined classifiers for multiple-valued functions to overcome the variable partitioning problem which allows finding the minimal column multiplicity and consequently to find high quality decompositions leading to good learning. The classifier gives very good accuracy results when tested on multi-valued Machine Learning benchmarks from the UC Irvine repository.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"23 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120824575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Symmetric Paraconsistent Quantum Logic 对称副一致量子逻辑
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00014
N. Kamide
{"title":"Symmetric Paraconsistent Quantum Logic","authors":"N. Kamide","doi":"10.1109/ISMVL51352.2021.00014","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00014","url":null,"abstract":"In this study, a new logic called symmetric paracon-sistent quantum logic (SPQL) is introduced as a dual monose-quent system, which is a restricted and indexed sequent calculus. The logic SPQL is regarded as an extension and generalization of Dalla Chiara and Giuntini's paraconsistent quantum logic (PQL). Theorems for syntactically and semantically embedding SPQL into PQL and vice versa are proved. Additionally, cut-elimination, symmetry-elimination, contraposition-elimination, and algebraic-completeness theorems are proved for SPOL.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117202111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Remarks on Particular Properties of Ternary Bent Functions and Construction Algorithms 关于三元弯曲函数的特殊性质及构造算法的评述
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00011
R. Stankovic, M. Stankovic, C. Moraga, J. Astola
{"title":"Remarks on Particular Properties of Ternary Bent Functions and Construction Algorithms","authors":"R. Stankovic, M. Stankovic, C. Moraga, J. Astola","doi":"10.1109/ISMVL51352.2021.00011","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00011","url":null,"abstract":"Binary bent functions have a strictly specified number of non-zero values. In the same way, ternary bent functions satisfy certain requirements on the elements of their value vectors. These requirements can be used to specify six classes of ternary bent functions. Classes are mutually related by encoding of function values. Functions within a class are mutually related by permutation of elements in their function vectors. Given a basic ternary bent function, other functions in the same class can be constructed by permutation matrices having a block structure similar to that of the factor matrices appearing in the Good-Thomas decomposition of Cooley-Tukey Fast Fourier transform and related algorithms. Conversion of function vectors into matrices or equivalent matrix-valued vectors of smaller length leads to the redistribution of space complexity of related manipulation algorithms. In this matrix representations, construction of other bent functions from a given known bent function is performed by using either properties of bent functions or by manipulation of such representations in terms of FFT-like permutation matrices of dimensions smaller than the length of the function vector of the initial bent functions.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122297136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory 多隧道磁阻自旋电子非易失性四元存储器
2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2021-05-01 DOI: 10.1109/ISMVL51352.2021.00037
Abdolah Amirany, M. H. Moaiyeri, Kian Jafari
{"title":"MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory","authors":"Abdolah Amirany, M. H. Moaiyeri, Kian Jafari","doi":"10.1109/ISMVL51352.2021.00037","DOIUrl":"https://doi.org/10.1109/ISMVL51352.2021.00037","url":null,"abstract":"Multi-value logic (MVL) is one of the options considered by researchers to overcome the limitations of the conventional binary logic because of their remarkable features such as lower transmission power consumption, lower area, interconnect, and pins. Quaternary logic is one of the forms of MVLs that has received special attention due to its compatibility with binary logic. In this paper, a quaternary non-volatile memory cell is designed and simulated using the threshold voltage tunability feature of gate-all-around carbon nanotube field-effect transistor transistors (GAA-CNTFET) and nonvolatile property of the magnetic tunnel junctions (MTJ). The simulation results show that while our proposed quaternary memory occupies a smaller area than the existing non-volatile quaternary memory, it consumes 31% and 33% lower average and static power, respectively. The Monte-Carlo simulations also show the correct operation of the proposed memory even in the presence of process variations.","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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