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Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)最新文献

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Fast self-recovering controllers 快速自恢复控制器
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670883
Andre Hertwig, S. Hellebrand, H. Wunderlich
{"title":"Fast self-recovering controllers","authors":"Andre Hertwig, S. Hellebrand, H. Wunderlich","doi":"10.1109/VTEST.1998.670883","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670883","url":null,"abstract":"A fast fault-tolerant controller structure is presented which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-tolerant controller structure utilizes the rollback hardware also for system mode and this way achieves performance improvements of more than 50% compared to controller structures made fault tolerant by conventional techniques, while the hardware overhead is often negligible. The proposed approach is compatible with state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129081652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient path selection for delay testing based on partial path evaluation 基于部分路径评估的延迟测试有效路径选择
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670867
S. Tani, M. Teramoto, T. Fukazawa, K. Matsuhiro
{"title":"Efficient path selection for delay testing based on partial path evaluation","authors":"S. Tani, M. Teramoto, T. Fukazawa, K. Matsuhiro","doi":"10.1109/VTEST.1998.670867","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670867","url":null,"abstract":"In this paper, we propose an efficient path selection method for path delay testing. The proposed method selects a very small set of paths for delay testing that covers all paths. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbance. In order to make precise judgement under this ambiguity, the delays of only unshared segments between the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths. Experimental results show the method can select about one percent of the paths selected by a conventional method without decreasing fault coverage.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128608239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
On synchronizing sequences and test sequence partitioning 同步序列和测试序列分区
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670864
I. Pomeranz, S. Reddy
{"title":"On synchronizing sequences and test sequence partitioning","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/VTEST.1998.670864","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670864","url":null,"abstract":"We consider two topics related to the testing of synchronous sequential circuits. The first topic deals with synchronizable circuits and their synchronizing sequences. Synchronizing sequences are important in facilitating the test generation process for detectable faults, and in identifying undetectable faults. They are also important in determining whether an undetectable fault can be removed from a circuit without affecting its normal operation. We show a class of faults for which a synchronizing sequence for the faulty circuit can be easily determined from the synchronizing sequence of the fault free circuit. We also consider circuits that have a reset mechanism, and show how reset can ensure that no single fault would cause the circuit to become unsynchronizable. The second topic we consider deals with test sequence partitioning to speed up static test compaction. We propose a procedure for partitioning a given test sequence into subsequences such that the cumulative fault coverage of all the subsequences, when applied as independent test sequences, is equal to the fault coverage of the original sequence. Each subsequence can then be compacted independently.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125893996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Estimation of error detection probability and latency of checking methods for a given circuit under check 对给定被检电路的检测方法的错误检测概率和延迟估计
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670891
Arsen Kuchukyan
{"title":"Estimation of error detection probability and latency of checking methods for a given circuit under check","authors":"Arsen Kuchukyan","doi":"10.1109/VTEST.1998.670891","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670891","url":null,"abstract":"A technique of sampling of input vectors (SIV) with statistical measurements is used for the estimation of error detection probability and fault latency of different checking methods. Application of the technique for Berger code, mod3 and parity checking for combinational circuits is considered. The experimental results obtained by a Pilot Software System are presented. The technique may be implemented as an overhead to an already existing fault simulator.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115046060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impedance mismatch and lumped capacitance effects in high frequency testing 高频测试中的阻抗失配和集总电容效应
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670875
I. Sylla, M. Slamani, B. Kaminska, F. Hossein, P. Vincent
{"title":"Impedance mismatch and lumped capacitance effects in high frequency testing","authors":"I. Sylla, M. Slamani, B. Kaminska, F. Hossein, P. Vincent","doi":"10.1109/VTEST.1998.670875","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670875","url":null,"abstract":"Working at high frequency adds to VLSI designers and test engineers many constraints. Many effects which are insignificant at low frequency domain have to be taken into account. These effects alternate considerably the precision of the test, introducing the a new challenge to the test community. The impedance mismatch between the circuit under test output impedance and the characteristic impedance of the transmission line as well as the effect of the lumped capacitance at the input of the tester comparator are among the most important effects. These two effects result as ringings, overshoot and timing delay. In this paper we present a method to eliminate the aberrations of the transmission line effects as well as the influence of the lumped capacitance at the input of the DUT thereby improving the precision of the rest.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"11 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120889521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A methodology for transforming memory tests for in-system testing of direct mapped cache tags 将内存测试转换为直接映射缓存标记的系统内测试的方法
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670897
Sultan M. Al-Harbi, S. Gupta
{"title":"A methodology for transforming memory tests for in-system testing of direct mapped cache tags","authors":"Sultan M. Al-Harbi, S. Gupta","doi":"10.1109/VTEST.1998.670897","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670897","url":null,"abstract":"While any efficient test developed for off-line testing of memory chips can be easily adapted for in-system testing of single level memory systems, no efficient methodology is known to transform such a test for in-system testing of multilevel memory systems that have one or more levels of cache. The main challenge is in transforming the known test to test the tags of the cache (testing of the data part of the cache is relatively straightforward). In this paper we present a general methodology to transform march tests for in-system testing of tags of direct mapped caches. The transformation has been used to obtain new versions of March B and March X tests. It is shown that the new versions of tests detect the same sets of faults in the cache tags as their original versions detect in memory chips. Finally, it is demonstrated that the proposed version of March B has significantly lower time complexity than previously proposed tests and can be applied without any modification of the memory system hardware.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127858730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A study on the utility of using expected quality level as a design for testability metric 期望质量水平作为可测试性度量设计的效用研究
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670880
Douglas Williams, F. Ferguson, T. Larrabee
{"title":"A study on the utility of using expected quality level as a design for testability metric","authors":"Douglas Williams, F. Ferguson, T. Larrabee","doi":"10.1109/VTEST.1998.670880","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670880","url":null,"abstract":"This paper develops a Physical Design for Test (PDFT) metric that is directly related to the expected quality level (QL) contribution of a cell to a circuit, and it details experimental results showing the usefulness of this metric in predicting the quality level contribution of a cell to circuits that have yet to be designed. The PDFT metric shows what QL increase can be expected for the circuit by changing the physical design of a component of the circuit.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134428996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sampling techniques of non-equally probable faults in VLSI systems VLSI系统中非等可能故障的采样技术
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670881
F. Gonçalves, João Paulo Teixeira
{"title":"Sampling techniques of non-equally probable faults in VLSI systems","authors":"F. Gonçalves, João Paulo Teixeira","doi":"10.1109/VTEST.1998.670881","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670881","url":null,"abstract":"The purpose of this paper is to present a novel methodology for defect-oriented (DO) fault sampling, and its implementation in a new extraction tool, lobs. The methodology is based on the statistics theory, and on the application of the concepts of estimation of totals over subpopulations and stratified sampling to the fault sampling problem. The proposed sampling methodology applies to non-equally probable DO faults, exhibiting a wide range of probabilities of occurrence, and leads to confidence intervals similar to the ones obtained with equally probable faults. ISCAS'85 benchmark circuits are laid out and lobs used to ascertain the results.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage 卡住双检测:一个基于卡住故障的故障模型，用于改进缺陷覆盖
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670882
I. Pomeranz, S. Reddy
{"title":"Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/VTEST.1998.670882","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670882","url":null,"abstract":"N-detection stuck-at test sets were shown to be effective in achieving high defect coverages for benchmark circuits. However, the definition of n-detection rest sets allows the same set of faults to be detected by several different tests, thus potentially detecting the same defects. We propose an extension of the n-detection model that alleviates this problem by considering m-tuples of faults and requiring that different tests would detect different m-tuples. We present experimental results to support this model.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126445524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Automatic insertion of scan structure to enhance testability of embedded memories, cores and chips 自动插入扫描结构，提高嵌入式存储器，核心和芯片的可测试性
Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI: 10.1109/VTEST.1998.670855
K. Zarrineh, S. Upadhyaya, P. Shephard
{"title":"Automatic insertion of scan structure to enhance testability of embedded memories, cores and chips","authors":"K. Zarrineh, S. Upadhyaya, P. Shephard","doi":"10.1109/VTEST.1998.670855","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670855","url":null,"abstract":"This paper describes a technology independent test synthesis framework to enhance the testability of embedded memories, cores and chips using extended LSSD boundary scan methodology. Extended LSSD boundary scan reuses functional storage elements and therefore introduces minimal test logic overhead and delay. Automatic insertion of this DFT methodology is particularly challenging since it involves identification and reconfiguration of the functional latches and logic transformations of I/O cells. Experimental results demonstrate the productivity gained using the proposed test synthesis framework as well as the overlead induced by the proposed DFT method.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134547261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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