2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)最新文献_第3页

Bits to BNNs: Reconstructing FPGA ML-IP with Joint Bitstream and Side-Channel Analysis 位到bnn:用联合比特流和侧信道分析重建FPGA ML-IP

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133375

Brooks Olney, Robert Karam

{"title":"Bits to BNNs: Reconstructing FPGA ML-IP with Joint Bitstream and Side-Channel Analysis","authors":"Brooks Olney, Robert Karam","doi":"10.1109/HOST55118.2023.10133375","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133375","url":null,"abstract":"Energy-efficient hardware acceleration platforms for edge deployment of artificial intelligence (AI) and machine learning (ML) applications has been an ongoing research endeavor. Many efforts have focused on optimizing the algorithms and compute structures for use in resource-constrained hardware such as field-programmable gate arrays (FPGAs). Indeed, the difficult nature of crafting the best model makes the ML model itself a valuable intellectual property (IP) asset. This can be problematic, as the IP can now be exposed to an attacker through physical interfaces, enabling threats from side-channel analysis (SCA) attacks. One of the more devastating attacks is the model extraction attack, which threatens piracy and cloning of the valuable IP. While the problem of SCA-based model extraction on FPGA-deployed neural networks has been well-studied, it does not capture the full picture of what vulnerabilities may be present in those platforms. In this paper, we demonstrate how bitstream analysis can be used to obtain neural network parameters and connectivity information from block RAMs (BRAMs). We leverage the knowledge gleaned from the bitstream to mount a power SCA attack to further refine the network reconstruction effort. This is the first method that has approached the problem of ML-IP theft from the angle of FPGA bitstream analysis and suggests that further work is needed to improve security assurance for edge intelligence.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Privacy-Preserving Protocol Level Approach to Prevent Machine Learning Modelling Attacks on PUFs in the Presence of Semi-Honest Verifiers 在半诚实验证者存在的情况下防止puf受到机器学习建模攻击的隐私保护协议级方法

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133804

Owen Millwood, Hongming Fei, P. Gope, Oğuz Narlı, M. K. Pehlivanoglu, E. Kavun, B. Sikdar

{"title":"A Privacy-Preserving Protocol Level Approach to Prevent Machine Learning Modelling Attacks on PUFs in the Presence of Semi-Honest Verifiers","authors":"Owen Millwood, Hongming Fei, P. Gope, Oğuz Narlı, M. K. Pehlivanoglu, E. Kavun, B. Sikdar","doi":"10.1109/HOST55118.2023.10133804","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133804","url":null,"abstract":"With the ubiquitous and distributed nature of the Internet-of-Things (IoT), various qualities of traditional communication methods for end devices and their verifiers prove insufficient in solving the challenges this new paradigm faces. Many new hardware and software technologies are proposed in an attempt to provide IoT systems with desired security properties while meeting performance requirements. Physically Unclonable Functions (PUFs) are one such technology receiving particular interest from the wider research community by promising to provide low-cost and highly secure key data to enable lightweight authentication protocols for devices operating over publicly accessible networks. PUFs have been the target of Machine Learning Modelling Attacks (ML-MA), which aim to clone the intrinsic behaviour of the PUF to undermine their security. While many PUF-based schemes have been proposed to defend against adversaries who are guaranteed to be dishonest, an area which has not seen significant consideration is one where a normal communication participant cannot always be assumed to act honestly. To the best of our knowledge, this work is the first to consider the concept of ‘semi-honest verifier’ for PUFbased authentication, taking initial steps to shed light on this prominent issue in IoT by proposing a privacy-preserving mutual authentication protocol which considers security against MLMA in the presence of such verifiers. Furthermore, this work describes hardware-level considerations for PUF obfuscation by utilising a combination of strong PUF, configurable One-Way Function (OWF) and secure DRAM-PUF and is, therefore, one of the first to integrate PUF obfuscation comprehensively at the protocol level.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129499423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance 处理器模糊与控制和状态寄存器指导

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133714

Sadullah Canakci, Chathura Rajapaksha, Leila Delshadtehrani, A. Nataraja, Michael B. Taylor, Manuel Egele, Ajay Joshi

{"title":"ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance","authors":"Sadullah Canakci, Chathura Rajapaksha, Leila Delshadtehrani, A. Nataraja, Michael B. Taylor, Manuel Egele, Ajay Joshi","doi":"10.1109/HOST55118.2023.10133714","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133714","url":null,"abstract":"As the complexity of modern processors has increased over the years, developing effective verification strategies to identify bugs prior to manufacturing has become critical. Inspired by software fuzzing, a technique commonly used for software testing, multiple recent works use hardware fuzzing for the verification of Register-Transfer Level (RTL) designs. However, these works suffer from several limitations such as lack of support for widelyused Hardware Description Languages (HDLs) and misleading coverage-signals that misidentify ‘‘interesting’’ inputs. Towards overcoming these shortcomings, we present ProcessorFuzz, a processor fuzzer that guides the fuzzer with a novel CSR-transition coverage metric. ProcessorFuzz monitors the transitions in Control and Status Registers (CSRs) as CSRs are in charge of controlling and holding the state of the processor. Therefore, transitions in CSRs indicate a new processor state, and guiding the fuzzer based on this feedback enables ProcessorFuzz to explore new processor states. We evaluated ProcessorFuzz with three real-world opensource processors — Rocket, BOOM, and BlackParrot. ProcessorFuzz triggered a set of ground-truth bugs $1.23 times$ faster (on average) than DIFUZZRTL. Moreover, our experiments exposed 8 new bugs across the three RISC-V cores and one new bug in a reference model. All nine bugs were confirmed by the developers of the corresponding projects.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133217466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Towards Secure Classical-Quantum Systems 迈向安全的经典量子系统

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133344

D. Volya, Tao Zhang, Nashmin Alam, M. Tehranipoor, P. Mishra

{"title":"Towards Secure Classical-Quantum Systems","authors":"D. Volya, Tao Zhang, Nashmin Alam, M. Tehranipoor, P. Mishra","doi":"10.1109/HOST55118.2023.10133344","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133344","url":null,"abstract":"Quantum computing has emerged as a promising paradigm, offering significant advancements in solving complex problems that are intractable for classical computers. These systems often involve integrated classical-quantum architectures, where classical components control and communicate with quantum devices. While this integration unlocks the potential of quantum computing, it also introduces new security vulnerabilities and challenges that must be addressed to ensure secure and reliable classical-quantum computing. This paper provides a comprehensive overview of the security concerns related to classical-quantum systems and discusses potential countermeasures. Specifically, we first investigate secure communication with a quantum device through side-channel analysis of post-quantum encryption algorithms. Next, we analyze security vulnerabilities in quantum devices. Finally, we explore mitigation strategies as well as the role of quantum compilation for securing quantum devices. By examining and addressing these critical security concerns, we aim to contribute to the development of a secure and robust foundation for the future of quantum computing. This work will be a stepping stone in secure and trustworthy deployment of integrated classicalquantum systems across various application domains.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"49 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Security Order of Gate-Level Masking Schemes 门级屏蔽方案的安全顺序

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133208

Sofiane Takarabt, Javad Bahrami, Mohammad Ebrahimabadi, S. Guilley, Naghmeh Karimi

{"title":"Security Order of Gate-Level Masking Schemes","authors":"Sofiane Takarabt, Javad Bahrami, Mohammad Ebrahimabadi, S. Guilley, Naghmeh Karimi","doi":"10.1109/HOST55118.2023.10133208","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133208","url":null,"abstract":"Masking schemes have been introduced to thwart side-channel attacks. In software applications, attackers can measure leakage at several points in time and combine them to defeat the masking. In hardware gate-level masking, all shares of a masked variable are manipulated at the same time in a nanoscale circuit. In this article, we focus on setups where the attacker uses one mesoscopic probe, which measures an aggregated leakage of all shares. We consider masking schemes where each bit is randomly split (by XOR) into so-called shares (two or more). We analyze two interesting case studies about the interrelationship of attack order vs. the number of shares. First of all, we show that when the unique probe is measuring the sum of each share’s individual leakage (so-called Hamming weight model), one measurement can reveal the sensitive unshared value, provided the attacker is able to determine the leakage’s least significant bit. Second, we analyze a hardware masking belonging to threshold schemes. Such schemes require fulfilling a so-called incompleteness property, whereby some input shares must be absent from output shares. We analyze a first-order incomplete scheme, i.e., where the number of missing input shares is equal to one. In schemes such as threshold implementation, this requires the number of shares to be strictly more than two. Hence the natural question is whether such a scheme would resist highorder attacks of order also strictly more than two? We answer by the negative, and show that the lowest attack order is two: the security of such a masking scheme is governed by the order of incompleteness and not by the number of shares. We verify our findings using four different sets of experiments including theoretical analysis, digital simulation, HSpice simulation and also real-silicon (FPGA emulation).","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121487661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

VPP: Privacy Preserving Machine Learning via Undervolting VPP:通过欠电压保护隐私的机器学习

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133266

Md. Shohidul Islam, Behnam Omidi, Ihsen Alouani, Khaled N. Khasawneh

{"title":"VPP: Privacy Preserving Machine Learning via Undervolting","authors":"Md. Shohidul Islam, Behnam Omidi, Ihsen Alouani, Khaled N. Khasawneh","doi":"10.1109/HOST55118.2023.10133266","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133266","url":null,"abstract":"Machine Learning (ML) systems are susceptible to membership inference attacks (MIAs), which leak private information from the training data. Specifically, MIAs are able to infer whether a target sample has been used in the training data of a given model. Such privacy breaching concern motivated several defenses against MIAs. However, most of the state-of-theart defenses such as Differential Privacy (DP) come at the cost of lower utility (i.e, classification accuracy). In this work, we propose Privacy Preserving Volt $(V_{PP})$, a new lightweight inference-time approach that leverages undervolting for privacy-preserving ML. Unlike related work, VPP maintains protected models’ utility without requiring re-training. The key insight of our method is to blur the MIA differential analysis outcome by comprehensively garbling the model features using random noise. Unlike DP, which injects noise within the gradient at training time, VPP injects computational randomness in a set of layers’ during inference through carefully designed undervolting Specifically, we propose a bi-objective optimization approach to identify the noise characteristics that yield privacypreserving properties while maintaining the protected model’s utility. Extensive experimental results demonstrate that VPP yields a significantly more interesting utility/privacy tradeoff compared to prior defenses. For example, with comparable privacy protection on CIFAR-10 benchmark, VPP improves the utility by 32.93% over DP-SGD. Besides, while related noisebased defenses are defeated by label-only attacks, VPP shows high resilience to such adaptive MLA. More over, VPP comes with a by-product inference power gain of up to 61%. Finally, for a comprehensive analysis, we propose a new adaptive attacks that operate on the expectation over the stochastic model behavior. We believe that VPP represents a significant step towards practical privacy preserving techniques and considerably improves the state-of-the-art.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116488291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Targeted Bitstream Fault Fuzzing Accelerating BiFI on Large Designs 目标比特流故障模糊化加速大型设计中的bii

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133494

Susanne Engels, Maik Ender, C. Paar

{"title":"Targeted Bitstream Fault Fuzzing Accelerating BiFI on Large Designs","authors":"Susanne Engels, Maik Ender, C. Paar","doi":"10.1109/HOST55118.2023.10133494","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133494","url":null,"abstract":"Fault injection attacks are a powerful instrument in an attacker’s toolbox to extract secret keys from cryptographic primitives. Generally, detailed information about the implementation and platform is needed to conduct such an attack in a meaningful fashion. With Bitstream Fault Injection (BiFI), Swierczynski et al. demonstrated that even without any prior knowledge, an adversary could use bitstream faults to disclose the secret key of cryptographic implementations on FPGAs. With a brute-force strategy, an extensive set of faulty bitstreams is generated by manipulating the FPGA’s LUTs, some of which enable the adversary to attack the design successfully. The drawback of BiFI is that its runtime scales with the design size because of aforementioned brute-force approach. Hence, it can be prohibitively slow, e.g., months, for large state-of-the-art FPGAs.In this work, we present Targeted Bitstream Fault Fuzzing (TBFF), which accelerates BiFI by identifying candidates of vulnerable LUTs using automated netlist reverse-engineering algorithms. Hence, the goal of TBFF is to combine the best of both worlds: TBFF automatically identifies small but crucial structures that are part of most cryptographic primitives, such as counters, done signals, or SBoxes. Introducing faults in these structures often instantly results in faulty behavior that can be exploited to recover the secret key. As a result, instead of brute-forcing, only a few targeted bitstream manipulations are needed to recover the secret key with the marginal overhead of identifying the relevant areas. Extrapolating this result for large-scale designs, TBFF can be conducted in minutes compared to months using the previous brute-force approach. In various case studies, we demonstrate the efficacy of our attack by attacking several AES designs.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128099170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware-Software Co-design for Side-Channel Protected Neural Network Inference 边信道保护神经网络推理的软硬件协同设计

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-05-01 DOI: 10.1109/HOST55118.2023.10133716

Anuj Dubey, Rosario Cammarota, Avinash L. Varna, Raghavan Kumar, Aydin Aysu

{"title":"Hardware-Software Co-design for Side-Channel Protected Neural Network Inference","authors":"Anuj Dubey, Rosario Cammarota, Avinash L. Varna, Raghavan Kumar, Aydin Aysu","doi":"10.1109/HOST55118.2023.10133716","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133716","url":null,"abstract":"Physical side-channel attacks are a major threat to stealing confidential data from devices. There has been a recent surge in such attacks on edge machine learning (ML) hardware to extract the model parameters. Consequently, there has also been work, although limited, on building corresponding defenses against such attacks. Current solutions take either fully software-or fully hardware-centric approaches, which are limited in performance and flexibility, respectively. In this paper, we propose the first hardware-software co-design solution for building side-channel-protected ML hardware. Our solution targets edge devices and addresses both performance and flexibility needs. To that end, we develop a secure RISCV-based coprocessor design that can execute a neural network implemented in C/C++. Our coprocessor uses masking to execute various neural network operations like weighted summations, activation functions, and output layer computation in a sidechannel secure fashion. We extend the original RV32I instruction set with custom instructions to control the masking gadgets inside the secure coprocessor. We further use the custom instructions to implement easy-to-use APIs that are exposed to the end-user as a shared library. Finally, we demonstrate the empirical sidechannel security of the design up to 1M traces.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127208908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

EC-CFI: Control-Flow Integrity via Code Encryption Counteracting Fault Attacks EC-CFI:通过代码加密对抗故障攻击的控制流完整性

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2023-01-31 DOI: 10.1109/HOST55118.2023.10132915

Pascal Nasahl, Salmin Sultana, Hans Liljestrand, Karanvir Grewal, Michael F. Lemay, David Durham, David Schrammel, S. Mangard

{"title":"EC-CFI: Control-Flow Integrity via Code Encryption Counteracting Fault Attacks","authors":"Pascal Nasahl, Salmin Sultana, Hans Liljestrand, Karanvir Grewal, Michael F. Lemay, David Durham, David Schrammel, S. Mangard","doi":"10.1109/HOST55118.2023.10132915","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10132915","url":null,"abstract":"Fault attacks enable adversaries to manipulate the controlflow of security-critical applications. By inducing targeted faults into the CPU, the software’s call graph can be escaped and the control-flow can be redirected to arbitrary functions inside the program. To protect the control-flow from these attacks, dedicated fault control-flow integrity (CFI) countermeasures are commonly deployed. However, these schemes either have high detection latencies or require intrusive hardware changes. In this paper, we present EC-CFI, a software-based cryptographically enforced CFI scheme with no detection latency utilizing hardware features of recent Intel® platforms. Our EC-CFI prototype is designed to prevent an adversary from escaping the program’s call graph using faults by encrypting each function with a different key before execution. At runtime, the instrumented program dynamically derives the decryption key, ensuring that the code only can be successfully decrypted when the program follows the intended call graph. To enable this level of protection on Intel® commodity systems, we combine Intel®’s TME-MK with the virtualization technology to achieve function-granular encryption. We open-source our custom LLVM-based toolchain automatically protecting arbitrary programs with EC-CFI. Furthermore, we evaluate EPT aliasing with the SPEC CPU2017 and Embench- IoT benchmarks and discuss and evaluate potential TME-MK hardware changes minimizing runtime overheads.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122432931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fast Fingerprinting of Cloud-based NISQ Quantum Computers 基于云的NISQ量子计算机的快速指纹识别

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-11-15 DOI: 10.1109/HOST55118.2023.10133778

Kaitlin N. Smith, Joshua Viszlai, Lennart Maximilian Seifert, Jonathan M. Baker, Jakub Szefer, F. Chong

{"title":"Fast Fingerprinting of Cloud-based NISQ Quantum Computers","authors":"Kaitlin N. Smith, Joshua Viszlai, Lennart Maximilian Seifert, Jonathan M. Baker, Jakub Szefer, F. Chong","doi":"10.1109/HOST55118.2023.10133778","DOIUrl":"https://doi.org/10.1109/HOST55118.2023.10133778","url":null,"abstract":"Cloud-based quantum computers have become a reality with a number of companies allowing for cloud-based access to their machines with tens to more than 100 qubits. With easy access to quantum computers, quantum information processing will potentially revolutionize computation, and superconducting transmon-based quantum computers are among some of the more promising devices available. Cloud service providers today host a variety of these and other prototype quantum computers with highly diverse device properties, sizes, and performances. The variation that exists in today‘s quantum computers, even among those of the same underlying hardware, motivate the study of how one device can be clearly differentiated and identified from the next. As a case study, this work focuses on the properties of 25 IBM superconducting, fixed-frequency transmon-based quantum computers that range in age from a few months to approximately 2.5 years. Through the analysis of current and historical quantum computer calibration data, this work uncovers key features within the machines, primarily frequency characteristics of transmon qubits, that can serve as a basis for a unique hardware fingerprint of each quantum computer.","PeriodicalId":128125,"journal":{"name":"2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"409 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1