{"title":"Design of Road Surface Lighting System for Rear Lamp using Automotive Ultrasonic Sensor","authors":"Donghee Han, Hyo Bin Choi, Y. Kim","doi":"10.1109/ISOCC.2018.8649888","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649888","url":null,"abstract":"There are quite a lot of accidents with pedestrians when backing a car. To prevent such accidents, recently, road surface lighting has appeared in the automotive industry. This technology is used to inform pedestrians that the vehicle is approaching by projecting light onto the road surface. In this paper, we propose the technology that changes a light pattern according to pedestrian’s position to improve his visibility by linking existing automotive ultrasonic sensors and road surface lighting module.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"171 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126023275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyunyoung Oh, Junmo Park, Myonghoon Yang, Dongil Hwang, Y. Paek
{"title":"Design of a Generic Security Interface for RISC-V Processors and its Applications","authors":"Hyunyoung Oh, Junmo Park, Myonghoon Yang, Dongil Hwang, Y. Paek","doi":"10.1109/ISOCC.2018.8649968","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649968","url":null,"abstract":"In this paper, we propose the design of a generic security interface for RISC-V. This interface increases flexibility of security modules by creating an environment that can operate independently on a host processor. We also present an application using this interface for the memory protection. To check the feasibility of our idea, we implement an early prototype where a RISC-V processor is connected with the proposed hardware components using our interface. The empirical results show that our security interface has enabled a security module operated independently of the processor with no performance and low area overhead.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient Implementation of Multiple Interleavers in IDMA for 5G","authors":"B. Y. Kong, I. Park","doi":"10.1109/ISOCC.2018.8649984","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649984","url":null,"abstract":"This paper presents an efficient implementation of multiple interleavers in interleave division multiple access (IDMA) for the 5G telecommunication. Rather than focusing on designing a single interleaver efficiently, in this paper, all the interleavers in an IDMA system are designed as a whole. More specifically, the interleaving formulae of multiple interleavers are mapped to a multiple constant multiplication problem, and common subexpressions are eliminated from the adder tree. As a result, the proposed architecture replaces costly multipliers with a similar number of adders, effectively reducing the hardware resources required to implement an IDMA system.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122858578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Test Methodology for Neural Computing Unit","authors":"Minho Cheong, Ingeol Lee, Sungho Kang","doi":"10.1109/ISOCC.2018.8649896","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649896","url":null,"abstract":"As convolutional neural networks (CNN) has been widely employed in deep learning applications, the accelerator for CNN has been proposed. Neural computing unit (NCU), which is an accelerator for CNN, includes thousands of identical cores named multiplier and accumulate (MAC), so testing NCU with the conventional methods are inefficient. This paper proposes a novel method to test NCU by applying test patterns for a MAC to all MACs in NCU. The experimental results indicate that the new method reduces test time to 1.38% and test data volume to 0.03%.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Real-time Tracking Algorithm for Human Following Mobile Robot","authors":"T. Tsai, Chia-Hsiang Yao","doi":"10.1109/ISOCC.2018.8649982","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649982","url":null,"abstract":"The ability to detect and track specific people is considered a key prerequisite for serving mobile robots. This paper presents a tracker using a binocular camera capable of tracking a specific human in both indoor and outdoor environments. The proposed tracker detects the target with the combination of human detection, color histogram, and block matching algorithm (BMA). When the color of the object is similar, the position of the object is determined by the predictor of the Kalman filter. Finally, the mobile robot is controlled based on the depth information of the target object. The effectiveness of the system is verified by human experiments in indoor and outdoor environments.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133638994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain","authors":"Hyeonchan Lim, Seokjun Jang, Sungho Kang","doi":"10.1109/ISOCC.2018.8649930","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649930","url":null,"abstract":"This paper presents a simulation-based scan chain diagnosis algorithm for double faults in a scan chain. With an ordinary flush test pattern, only the last fault can be observed while the others are masked by the last fault. Considering the multiple faults, the forward fault and the rearward fault are decided by analyzing signatures of a faulty chain and good chains, separately. The results of analysis are upper bound (rearward fault) and lower bound (forward fault). If only one fault exists, there is only a candidate in the boundary. The proposed technique can be applied for both stuck-at and transition faults. ISCAS’89 benchmark circuits verify the proposed method and the experimental results show that the diagnosis resolution is increased compared to the conventional method.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of 3D Hand Gesture Recognition System using FPGA","authors":"T. Tsai, Yuan-Chen Ho, Yih-Ru Tsai","doi":"10.1109/ISOCC.2018.8649939","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649939","url":null,"abstract":"In this paper, a VLSI design with dual-camera to construct the depth map and recognize hand gestures was proposed. The proposed system adopts adaptive depth filter which can separate foreground to segment the interesting object under complicated environment. We also proposed dynamic gesture recognition by using depth and coordinate information. The system contains one static gesture and two dynamic gestures and has been implemented in FPGA and the average accuracy with each gesture is 83.98%.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"108 5-6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134179916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyunghyun Lim, Minsoo Choi, M. Aung, Kyunghwan Kim, Ji-Seong Kim, R. Baek, Ho-Jin Song, T. T. Kim, Byungsub Kim
{"title":"Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects","authors":"Kyunghyun Lim, Minsoo Choi, M. Aung, Kyunghwan Kim, Ji-Seong Kim, R. Baek, Ho-Jin Song, T. T. Kim, Byungsub Kim","doi":"10.1109/ISOCC.2018.8649925","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649925","url":null,"abstract":"This paper experimentally verifies a simple, intuitive, and accurate closed-form transfer function model for diverse high-speed interconnects for the first time. Recently, an approximate closed-form transfer function model, which is simple, intuitive, and accurate, as well as applicable to diverse high-speed interconnects, was proposed. However, because the model was only verified by SPICE simulation, the experimental verification is required to guarantee the reliability of the model in practical high-speed interconnects. To this end, an example interconnect was designed and fabricated, and its characteristic impedance and propagation constant were extracted. Then, the transfer function calculated from the extracted parameters by using the model was compared with measurement. The result shows that the model can describe the behavior of the fabricated example interconnect and thus is reliable in practical high-speed interconnects.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133747787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Prateek Manocha, Ayush Kumar, Jameel Ahmed Khan, Hyunchu Shin
{"title":"Korean Traffic Sign Detection Using Deep Learning","authors":"Prateek Manocha, Ayush Kumar, Jameel Ahmed Khan, Hyunchu Shin","doi":"10.1109/ISOCC.2018.8649887","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649887","url":null,"abstract":"In this paper, we present a new optimized architecture modified from YOLOv3 to detect three different classes of challenging Korean Traffic Sign Detection (KTSD) dataset. We optimized the new neural network called TS detector with denser grid size, and optimized anchor box size to detect prohibitory, mandatory, and danger classes of KTSD dataset. We trained this architecture on our Korean traffic sign dataset to achieve the mAP value of 86.61%. Our results are significantly better than original YOLOv3 and D-Patches algorithm in terms of mAP value and CPU time.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129028575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junichi Suzuki, J. Yamashita, M. Hanyu, Masamichi Ido, Tatsuya Saito, Yasuhiro Nakashima, M. Hayashikoshi, Yukiyoshi Kiyota
{"title":"A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory","authors":"Junichi Suzuki, J. Yamashita, M. Hanyu, Masamichi Ido, Tatsuya Saito, Yasuhiro Nakashima, M. Hayashikoshi, Yukiyoshi Kiyota","doi":"10.1109/ISOCC.2018.8649907","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649907","url":null,"abstract":"As the demand and production volume for embedded flash MCUs increase, their flash memory test time reduction is getting more important. Among them, trimming test occupies to a certain extent. To decrease it, a dedicated on-chip test circuit of a current comparator can be an answer, but such a current comparator tends to consume large area when high precision is needed. In this paper, we proposed a new current judgement circuit for reference current trimming, of small area and high precision. A test chip of 110 nm process embedded flash memory for MCUs with the new trimming circuit has been fabricated and the new circuit effects have been confirmed by the test chip. The 0.59 percent of Flash macro size can be reduced with this proposed auto-trimming circuit.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116221577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}