International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004.最新文献_第2页

Facilitating reuse in hardware models with enhanced type inference 通过增强的类型推断促进硬件模型中的重用

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016744

Manish Vachharajani, Neil Vachharajani, S. Malik, David I. August

引用次数: 0

A novel deadlock avoidance algorithm and its hardware implementation 一种新的死锁避免算法及其硬件实现

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016769

J. Lee, V. Mooney

引用次数: 12

Current flattening in software and hardware for security applications 目前安全应用软件和硬件的扁平化

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016773

R. Muresan, C. Gebotys

引用次数: 29

Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking 利用全局伪同步局部同步时钟降低二维网格noc的功耗和延迟

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016764

E. Nilsson, Johnny Öberg

{"title":"Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking","authors":"E. Nilsson, Johnny Öberg","doi":"10.1145/1016720.1016764","DOIUrl":"https://doi.org/10.1145/1016720.1016764","url":null,"abstract":"One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem have been proposed over the years. For networks-on-chip (NoC), where computational resources are organised in a 2-D mesh connected together through switches in an on-chip interconnection network, another possibility exists: globally pseudochronous locally synchronous clock distribution. We present a clocking scheme for NoCs that we call globally pseudochronous locally synchronous, in which we distribute a clock with a constant phase difference between the switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths data motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case. The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which leads to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.","PeriodicalId":127038,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128981040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

Multi-objective mapping for mesh-based NoC architectures 基于网格的NoC体系结构多目标映射

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016765

G. Ascia, V. Catania, M. Palesi

引用次数: 178

Fast exploration of bus-based on-chip communication architectures 快速探索基于总线的片上通信架构

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016778

S. Pasricha, N. Dutt, M. Ben-Romdhane

{"title":"Fast exploration of bus-based on-chip communication architectures","authors":"S. Pasricha, N. Dutt, M. Ben-Romdhane","doi":"10.1145/1016720.1016778","DOIUrl":"https://doi.org/10.1145/1016720.1016778","url":null,"abstract":"As a result of improvements in process technology, more and more components are being integrated into a single system-on-chip (SoC) design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It therefore becomes extremely important for designers to explore the communication space early in the design flow. Traditionally, pin-accurate bus cycle accurate (PA-BCA) models were used for exploring the communication space. To speed up simulation, transaction based bus cycle accurate (T-BCA) models have been proposed, which borrow concepts found in the transaction level modeling (TLM) domain. The cycle count accurate at transaction boundaries (CCATB) modeling abstraction was introduced for fast communication space exploration. In This work, we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of a case study involving an AMBA 2.0 based SoC subsystem used in the multimedia application domain. We also analyze how the achieved simulation speedup scales with design complexity and show that SoC designs modeled at the CCATB level simulate 120% faster than PA-BCA and 67% faster than T-BCA models on average.","PeriodicalId":127038,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115257915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 69

Analytical models for leakage power estimation of memory array structures 存储阵列结构泄漏功率估计的分析模型

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016757

M. Mamidipaka, K. Khouri, N. Dutt, M. Abadir

{"title":"Analytical models for leakage power estimation of memory array structures","authors":"M. Mamidipaka, K. Khouri, N. Dutt, M. Abadir","doi":"10.1145/1016720.1016757","DOIUrl":"https://doi.org/10.1145/1016720.1016757","url":null,"abstract":"There is a growing need for accurate power models at the system level. Memory structures such as caches, branch target buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.","PeriodicalId":127038,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114645634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

A timing-accurate HW/SW cosimulation of an ISS with SystemC 国际空间站与SystemC定时精确的软硬件联合仿真

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016759

L. Formaggio, F. Fummi, G. Pravadelli

引用次数: 18

Compiler-directed code restructuring for reducing data TLB energy 编译器导向的代码重组，以减少数据TLB能量

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016747

M. Kandemir, I. Kadayif, G. Chen

引用次数: 23

Efficient exploration of on-chip bus architectures and memory allocation 片上总线架构和内存分配的有效探索

International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004. Pub Date : 2004-09-08 DOI: 10.1145/1016720.1016779

Sungchan Kim, Chaeseok Im, S. Ha

引用次数: 21