A. Marcelli, E. Sánchez, Luca Sasselli, Giovanni Squillero
{"title":"On the Mitigation of Hardware Trojan Attacks in Embedded Processors by Exploiting a Hardware-Based Obfuscator","authors":"A. Marcelli, E. Sánchez, Luca Sasselli, Giovanni Squillero","doi":"10.1109/IVSW.2018.8494850","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494850","url":null,"abstract":"Due to the complexity of digital circuits manufacturing, nowadays most semi-conductor companies outsource part of the fabrication process, reducing both the production costs and the time- to- market. However, as untrusted parties are involved in the production-chain, new security risks arise, and the threat of Hardware Trojans is a serious concern for the producers of embedded devices. In this paper, we propose an on-chip software obfuscator aiming to reduce the activation probability of malicious components through software. Using a completely transparent hardware based solution, with a limited hardware and time overhead, the sequence of instructions is modified, eventually defusing Trojan activation sequences, yet guaranteeing the original functionalities. The methodology was implemented in a modified version of the OR1200 processor core, using a set of programs from the MiBench test suit, to demonstrate the method suitability.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121288457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Property Based Formal Security Verification for Hardware Trojan Detection","authors":"Maoyuan Qin, Wei Hu, Dejun Mu, Yu Tai","doi":"10.1109/IVSW.2018.8494858","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494858","url":null,"abstract":"The design of modern computer hardware heavily relies on third-party intellectual property (IP) cores, which may contain malicious hardware Trojans that could be exploited by an adversary to leak secret information or take control of the system. Existing hardware Trojan detection methods either require a golden reference design for comparison or extensive functional testing to identify suspicious signals. In this paper, we propose a new formal verification method to verify the security of hardware designs. The proposed solution formalizes fine grained gate level information flow model for proving security properties of hardware designs in the Coq theorem prover environment. Compare with existing register transfer level (RTL) information flow security models, our model only needs to translate a small number of logic primitives to their formal representations without the need of supporting the rich RTL HDL semantics or dealing with complex conditional branch or loop structures. As a result, a gate level information flow model can be created at much lower complexity while achieving significantly higher precision in modeling the security behavior of hardware designs. We use the AES-T1700 benchmark from Trust-HUB to demonstrate the effectiveness of our solution. Experimental results show that our method can detect and pinpoint the Trojan.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121446903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Security Analysis of Chaotic Baker Maps","authors":"A. Elhamshary, Y. Ismail, Said Elkhamy","doi":"10.1109/IVSW.2018.8494880","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494880","url":null,"abstract":"This paper presents a detailed analysis of the security characteristics of chaotic Baker Maps and presents suggestions to improve its security characteristics. The number of possible keys for a baker map is derived using closed form solutions. It is shown that for a reasonable size baker map a large number of possible keys exists, making a brute force attack infeasible. However, it is shown that baker maps have very poor security characteristics under known attacks. Specifically, a baker map of size $N$ can be broken in $N$ iterations or less. This weakness can limit the usefulness of using baker maps as is in encryption. Modified techniques are needed to improve the security of baker maps, some of which are suggested in this paper.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131509806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hastings, Sean Jensen, Jeffrey B. Goeders, B. Hutchings
{"title":"Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs","authors":"A. Hastings, Sean Jensen, Jeffrey B. Goeders, B. Hutchings","doi":"10.1109/IVSW.2018.8494874","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494874","url":null,"abstract":"In modern FPGA design, 3rd-party IP is commonly used to reduce costs and time-to-market. However, the complexity of IP and associated CAD tools makes it easier for attackers to maliciously tamper with the IP (i.e. insert Hardware Trojans) in ways that are hard to detect. This work proposes techniques that allows a user to incorporate trusted 3rd-party IP into a design and verify that the incorporation occurs tamper-free. We present comparative results from utilizing this framework across a benchmark suite of 22 designs. We show that the approach reliably detects tampering without giving any false positives.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132926205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. D. Silva, E. Valea, M. Flottes, Sophie Dupuis, G. D. Natale, B. Rouzeyre
{"title":"A New Secure Stream Cipher for Scan Chain Encryption","authors":"M. D. Silva, E. Valea, M. Flottes, Sophie Dupuis, G. D. Natale, B. Rouzeyre","doi":"10.1109/IVSW.2018.8494852","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494852","url":null,"abstract":"The accessibility to the internal IP cores of Systems on Chip (SoC) provided by the testing infrastructures is a serious security threat. It has been known for many years that the scan chains can be exploited to retrieve secret keys of crypto-processors. Encryption of the scan chain content is one of the proposed techniques to overtake this threat. Many proposals are based on stream ciphers, due to their moderate area cost compared to that of block ciphers. Stream ciphers encrypt data serially with a keystream generated from an Initialization Vector (IV) and a secret key. Stream ciphers have a crucial limitation concerning the encryption of different data with the same keystream, called two times pad. Not enough caution in the IV and secret key management has been exercised in previous proposed works. In this paper, we show how the existing implementations can be exploited to perform a scan attack bypassing the encryption of the scan data. We also present a new implementation of scan chain encryption with a stream cipher, based on the IV generation by a True Random Number Generator (TRNG). Finally, we show that this new implementation is robust against the aforementioned attack.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126314852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architectural Diversity: Bio-Inspired Hardware Security for FPGAs","authors":"Shakil Mahmud, Brooks Olney, Robert Karam","doi":"10.1109/IVSW.2018.8494854","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494854","url":null,"abstract":"Security of computing systems has emerged as a major concern in today's society, as attacks on CPUs, ran-somware, and botnets are becoming all the more common. One of the primary enablers of these widespread attacks is the mass production of computer hardware. While this is beneficial for design, fabrication, and test, it leaves all devices with the same hardware vulnerable to the same attacks. In nature, diversity at the genetic level helps ensure survival of a species, and provides resilience to some individuals against certain pathogens. While diversity has been explored at the software level, its applicability to hardware is less obvious. This paper explores the application of mutating hardware, inspired by evolution in nature, to Field Programmable Gate Arrays, and provides examples of low-overhead modifications to a typical FPGA architecture that enables secure, mutating architectures for current- and next-generation FPGAs.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michael Werner, Bernhard Lippmann, Johanna Baehr, H. Graeb
{"title":"Reverse Engineering of Cryptographic Cores by Structural Interpretation Through Graph Analysis","authors":"Michael Werner, Bernhard Lippmann, Johanna Baehr, H. Graeb","doi":"10.1109/IVSW.2018.8494896","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494896","url":null,"abstract":"Reverse Engineering (RE) of integrated circuits (ICs) is generally defined as the recovery process of unknown system internals. While advanced solutions to extract gate-level netlists from a target device exist, the possibility of subsequent interpretation is limited, in particular in complex devices. This paper introduces a novel graph based method for identifying intellectual property (IP) blocks within an unstructured netlist by using graph analysis. Without prior knowledge of the targeting device, firstly, associated structural components, secondly, functional components and, thirdly, the initial design hierarchy will be identified by this method. Experimental results using realworld netlists including cryptographic cores show the efficiency and efficacy of the presented method.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"16 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130639357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Lightweight PUF-Based Authentication Protocol for IoT Devices","authors":"Yıldıran Yılmaz, S. Gunn, Basel Halak","doi":"10.1109/IVSW.2018.8494884","DOIUrl":"https://doi.org/10.1109/IVSW.2018.8494884","url":null,"abstract":"Conventional cryptographic solutions to the security are expensive in terms of computing resources (memory and processing capacity) and power consumption. They are not suitable for the Internet of Things devices that have constrained resources. In this regard, physically unclonable functions (PUFs) have become an increasingly popular technology for building secure authentication in these systems. In this paper, we propose lightweight PUF-based authentication protocol. This was implemented on a wireless sensor network constructed using the resource-limited IoT devices: Zolertia Zoul re-mote. The functionality of the proposed scheme was verified using a server-client configuration. Then power consumption and memory utilisation of the proposed protocol were estimated and compared with the existing solutions, namely: DTLS (datagram transport layer security) handshake protocol and UDP (user datagram protocol). Our results indicate that the proposed PUF based authentication saves up to 45% power and uses 12% less memory compared to DTLS handshake authentication.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127768468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Welcome message","authors":"Shiuh-An Shieh","doi":"10.1109/ivsw.2018.8494872","DOIUrl":"https://doi.org/10.1109/ivsw.2018.8494872","url":null,"abstract":"It is our great pleasure to welcome you to the third edition of the IEEE Conference on Dependable and Secure Computing (IDSC 2019). This year's conference continues its tradition of being the premier forum for the presentation of innovative research results, problem solutions, and new challenges in the field of dependable and secure computing. The mission of the conference is to share novel solutions that fulfil the needs of secure and dependable applications and services, and identify new directions for future research and development.","PeriodicalId":125301,"journal":{"name":"2018 IEEE 3rd International Verification and Security Workshop (IVSW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121208327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}