发布求助
文献互助 智能选刊 最新文献

Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems最新文献

筛选
英文 中文
On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures 基于Max-Plus代数的多核DSE调度的解析评价
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323979
Martín Letras, J. Falk, T. Schwarzer, J. Teich
{"title":"On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures","authors":"Martín Letras, J. Falk, T. Schwarzer, J. Teich","doi":"10.1145/3323439.3323979","DOIUrl":"https://doi.org/10.1145/3323439.3323979","url":null,"abstract":"Dataflow modeling is well suited for a wide variety of applications for multi-core architectures, e.g. signal processing and control domain. Additionally, Design Space Exploration (DSE) can be used to explore the distribution of tasks to resources and their scheduling to obtain optimized trade-off solutions between throughput and resource costs. However, the performance evaluation of an implementation candidate in particular via compilation and throughput measurement on the target hardware is prohibitively time-consuming. Thus, we propose to use a max-plus algebra-based analytic throughput calculation method in the initial DSE phase where a fast evaluation with low accuracy is sufficient to guide the search through the design space. However, this analysis neglects some real-world concerns like cache effects and scheduling overhead. Thus, a hybrid DSE is proposed where throughput measurements are taken later in the DSE to get more accurate throughput results for real-world platforms. Results show that our approach is able to find much higher throughput multi-core solutions within a given exploration time compared to a state-of-the-art DSE approach.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117348707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Can Flexible Multi-Core Scheduling Help to Execute Machine Learning Algorithms Resource-Efficiently? 灵活的多核调度是否有助于高效地执行机器学习算法?
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323986
Helena Kotthaus, Lea Schönberger, Andreas Lang, Jian-Jia Chen, P. Marwedel
{"title":"Can Flexible Multi-Core Scheduling Help to Execute Machine Learning Algorithms Resource-Efficiently?","authors":"Helena Kotthaus, Lea Schönberger, Andreas Lang, Jian-Jia Chen, P. Marwedel","doi":"10.1145/3323439.3323986","DOIUrl":"https://doi.org/10.1145/3323439.3323986","url":null,"abstract":"Machine learning techniques such as model-based optimization are frequently used to solve expensive problems. Since a sequential execution of these algorithms is time-intensive due to the problem complexity, several attempts have been made to parallelize existing approaches. However, no state-of-the-art technique is able to efficiently exploit the full potential of multi-core architectures up to now. In this work, we propose a flexible extension to the Resource-Aware Model-Based Optimization framework (RAMBO) adopting multi-core scheduling techniques, which allows to use the available resources in a more efficient way and thus reduces the time required to solve expensive optimization problems.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133288972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SYCL Code Generation for Multigrid Methods 多网格方法的SYCL代码生成
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323984
Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig
{"title":"SYCL Code Generation for Multigrid Methods","authors":"Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig","doi":"10.1145/3323439.3323984","DOIUrl":"https://doi.org/10.1145/3323439.3323984","url":null,"abstract":"Multigrid methods are fast and scalable numerical solvers for partial differential equations (PDEs) that possess a large design space for implementing their algorithmic components. Code generation approaches allow formulating multigrid methods on a higher level of abstraction that can then be used to derive a problem- and hardware-specific solutions. Since these problems have a considerable implementation variability, it is crucial to investigate a general mapping of core components in multigrid methods to the target software. With SYCL there exists a high-level C++ abstraction layer that is capable of targeting a multitude of architectures. We contribute a general way to map multigrid components to SYCL functionality and provide a performance evaluation for specific algorithmic components.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123471542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Global optimization of operand transfer fusion in heterogeneous computing 异构计算中操作数转移融合的全局优化
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323981
C. Kessler
{"title":"Global optimization of operand transfer fusion in heterogeneous computing","authors":"C. Kessler","doi":"10.1145/3323439.3323981","DOIUrl":"https://doi.org/10.1145/3323439.3323981","url":null,"abstract":"We consider the problem of minimizing, for a dataflow graph of kernel calls, the overall number of operand data transfers, and thus, the accumulated transfer startup overhead, in heterogeneous systems with non-shared memory. Our approach analyzes the kernel-operand dependence graph and reorders the operand arrays in memory such that transfers and memory allocations of multiple operands adjacent in memory can be merged, saving transfer startup costs and memory allocation overheads.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122217608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards Efficient Code Generation for Exposed Datapath Architectures 面向公开数据路径体系结构的高效代码生成
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323990
K. Vadivel, Roel Jordans, S. Stuijk, H. Corporaal, P. Jääskeläinen, Heikki O. Kultala
{"title":"Towards Efficient Code Generation for Exposed Datapath Architectures","authors":"K. Vadivel, Roel Jordans, S. Stuijk, H. Corporaal, P. Jääskeläinen, Heikki O. Kultala","doi":"10.1145/3323439.3323990","DOIUrl":"https://doi.org/10.1145/3323439.3323990","url":null,"abstract":"Coarse-grained reconfigurable architectures and other exposed datapath architectures such as transport-triggered architectures come with a high energy efficiency promise for accelerating data oriented workloads. Their main drawback results from the push of complexity from the architecture to the programmer; compiler techniques that allow starting from a higher-level programming language and generate code efficiently to such architectures robustly is still an open research area. In this article we survey the known main sources of challenges and outline a generic processor architecture template that covers the most common architecture variations along with a proposal for a common code generation framework for such challenging architectures.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133123402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compiler-Based Code Compression for Hard Real-Time Systems 硬实时系统中基于编译器的代码压缩
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323976
Kateryna Muts, Arno Luppold, H. Falk
{"title":"Compiler-Based Code Compression for Hard Real-Time Systems","authors":"Kateryna Muts, Arno Luppold, H. Falk","doi":"10.1145/3323439.3323976","DOIUrl":"https://doi.org/10.1145/3323439.3323976","url":null,"abstract":"Real-Time Systems often come with additional requirements apart from being functionally correct and adhering to their timing constraints. Another common additional optimization goal is to meet code size requirements. Code compression techniques might be utilized to meet code size constraints in embedded systems. We show how to extend a compiler targeting hard real-time systems by an asymmetric compiler-based code compression/decompression, where the compression is performed at the compilation time and the decompression takes place at the execution time. Moreover, experimental results show the impact of the decompression algorithm on the estimated Worst-Case Execution Time that is one of the key properties of hard real-time systems.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126366811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CIM-SIM: Computation In Memory SIMuIator 内存中的计算模拟器
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323989
Ali BanaGozar, K. Vadivel, S. Stuijk, H. Corporaal, Stephan Wong, Muath Abu Lebdeh, Jintao Yu, S. Hamdioui
{"title":"CIM-SIM: Computation In Memory SIMuIator","authors":"Ali BanaGozar, K. Vadivel, S. Stuijk, H. Corporaal, Stephan Wong, Muath Abu Lebdeh, Jintao Yu, S. Hamdioui","doi":"10.1145/3323439.3323989","DOIUrl":"https://doi.org/10.1145/3323439.3323989","url":null,"abstract":"Computation-in-memory reverses the trend in von-Neumann processors by bringing the computation closer to the data, to even within the memory array, as opposed to introducing new memory hierarchies to keep (frequently used) data closer to a central processing unit (CPU). In recent years, new non-volatile memory (NVM) technologies, e.g., memristor, PCM, etc., have proven that they can function as memories and perform computations on the stored data as well. In particular, when they are combined with a modest set of (digital) peripheral modules, a wider range of operations can be supported, e.g., vector matrix multiply and Boolean logic. In this paper, we are introducing the CIM-SIM, an open source simulator written in SystemC, which is capable of simulating the functional behaviour of such architectures. The architecture includes the definition of a set of technology-agnostic nano-instructions.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures 一种新的粗粒度可编程收缩体系结构映射方法
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323982
Elias Barbudo, Eva Dokládalová, T. Grandpierre, L. George
{"title":"A New Mapping Methodology for Coarse-Grained Programmable Systolic Architectures","authors":"Elias Barbudo, Eva Dokládalová, T. Grandpierre, L. George","doi":"10.1145/3323439.3323982","DOIUrl":"https://doi.org/10.1145/3323439.3323982","url":null,"abstract":"Coarse-grained programmable systolic architectures are designed to meet hard time constraints and provide high-performance computing. They consist of a set of programmable hardware resources with directed interconnections between them. The level of complexity of these architectures limits their re-usability. An automated mapping methodology is required to add a re-usability value to these architectures. In this work, we present a new list-scheduling based mapping methodology for coarse-grained programmable systolic architectures. We use a Directed Acyclic Graph to express the tasks and data dependency of the application as well as the hardware resources organization. We demonstrate that our approach can map different applications, provide a latency estimation and generate the configuration context. This approach could be the base for design space exploration and optimization tools for this family of architectures.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134305034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Favorable Adjustment of Periods for Reduced Hyperperiods in Real-Time Systems 实时系统中简化超周期的有利周期调整
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323975
Dominic Oehlert, Arno Luppold, H. Falk
{"title":"Favorable Adjustment of Periods for Reduced Hyperperiods in Real-Time Systems","authors":"Dominic Oehlert, Arno Luppold, H. Falk","doi":"10.1145/3323439.3323975","DOIUrl":"https://doi.org/10.1145/3323439.3323975","url":null,"abstract":"The hyperperiod defines the time span after which the temporal behavior of a periodical real-time system repeats. It is the key property which determines the complexity of both analysis and exhaustive simulation of a given system. Unfortunately, the hyperperiod may easily become very large. We introduce an ILP-based approach to modify the periods in a task set according to user constraints to retrieve an optimal solution for a drastically reduced hyperperiod.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"5 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memristors for Programmable Circuits Controlled by Embedded Systems 嵌入式系统控制的可编程电路忆阻器
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems Pub Date : 2019-05-27 DOI: 10.1145/3323439.3323985
Philipp Grothe, Jan Haase
{"title":"Memristors for Programmable Circuits Controlled by Embedded Systems","authors":"Philipp Grothe, Jan Haase","doi":"10.1145/3323439.3323985","DOIUrl":"https://doi.org/10.1145/3323439.3323985","url":null,"abstract":"Many embedded systems reside within bigger electrical systems. While the embedded system takes control over many aspects of the surrounding systems, the amount of possible control is set by the given configuration. This causes a divide between the flexibility provided by software and the unchanging nature of the encompassing hardware. The concept of programmable circuits seeks to bridge this gap. The use of memristors enables the changing of resistor values within a circuit without disassembly. The continuous, non-volatile variable resistor provides the possibility to reconfigure hardware circuits through external influences or even by software on the embedded system at run time. During the research, control of memristors by common microprocessors was achieved and a prototype was implemented to test the concept for use in a circuit classifying data streams.","PeriodicalId":125133,"journal":{"name":"Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130354922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书